Merge 84ae593a09 into 8be7c53ea0
GitHub
commit
a40690d23d
@ -0,0 +1,359 @@
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LOCATE COMP "ext_clk" SITE "K23";
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IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33;
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LOCATE COMP "ext_rst_n" SITE "N5";
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LOCATE COMP "gsrn" SITE "AB1";
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IOBUF PORT "ext_rst_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "gsrn" IO_TYPE=LVCMOS33;
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LOCATE COMP "uart0_txd" SITE "R24";
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LOCATE COMP "uart0_rxd" SITE "R26";
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IOBUF PORT "uart0_txd" IO_TYPE=LVCMOS33;
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IOBUF PORT "uart0_rxd" IO_TYPE=LVCMOS33;
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LOCATE COMP "led5_r_n" SITE "T23";
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LOCATE COMP "led5_g_n" SITE "R21";
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LOCATE COMP "led5_b_n" SITE "T22";
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IOBUF PORT "led5_r_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led5_g_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led5_b_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "led6_r_n" SITE "U21";
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LOCATE COMP "led6_g_n" SITE "W21";
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LOCATE COMP "led6_b_n" SITE "T24";
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IOBUF PORT "led6_r_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led6_g_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led6_b_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "led7_r_n" SITE "K21";
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LOCATE COMP "led7_g_n" SITE "K24";
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LOCATE COMP "led7_b_n" SITE "M21";
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IOBUF PORT "led7_r_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led7_g_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led7_b_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "led8_r_n" SITE "P21";
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LOCATE COMP "led8_g_n" SITE "R23";
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LOCATE COMP "led8_b_n" SITE "P22";
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IOBUF PORT "led8_r_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led8_g_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "led8_b_n" IO_TYPE=LVCMOS33;
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// We use USRMCLK instead for clk
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// LOCATE COMP "spi_flash_clk" SITE "U16";
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// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_cs_n" SITE "AA2";
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IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_mosi" SITE "AE2";
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IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_miso" SITE "AD2";
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IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_wp_n" SITE "AF2";
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IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_hold_n" SITE "AE1";
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IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33;
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// Ethernet
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LOCATE COMP "rgmii_clocks_rx" SITE "E11";
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LOCATE COMP "rgmii_clocks_tx" SITE "A12";
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LOCATE COMP "rgmii_rst_n" SITE "C13";
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LOCATE COMP "rgmii_int_n" SITE "B13";
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LOCATE COMP "rgmii_mdc" SITE "C11";
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LOCATE COMP "rgmii_mdio" SITE "A13";
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LOCATE COMP "rgmii_rx_ctl" SITE "A11";
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LOCATE COMP "rgmii_rx_data[0]" SITE "B11";
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LOCATE COMP "rgmii_rx_data[1]" SITE "A10";
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LOCATE COMP "rgmii_rx_data[2]" SITE "B10";
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LOCATE COMP "rgmii_rx_data[3]" SITE "A9";
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LOCATE COMP "rgmii_tx_ctl" SITE "C9";
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LOCATE COMP "rgmii_tx_data[0]" SITE "D8";
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LOCATE COMP "rgmii_tx_data[1]" SITE "C8";
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LOCATE COMP "rgmii_tx_data[2]" SITE "B8";
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LOCATE COMP "rgmii_tx_data[3]" SITE "A8";
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IOBUF PORT "rgmii_clocks_rx" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_clocks_tx" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_rst_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_int_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_mdc" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_mdio" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_rx_ctl" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_rx_data[0]" IO_TYPE=LVCMOS33 PULLMODE=UP;
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IOBUF PORT "rgmii_rx_data[1]" IO_TYPE=LVCMOS33 PULLMODE=UP;
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IOBUF PORT "rgmii_rx_data[2]" IO_TYPE=LVCMOS33 PULLMODE=UP;
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IOBUF PORT "rgmii_rx_data[3]" IO_TYPE=LVCMOS33 PULLMODE=UP;
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IOBUF PORT "rgmii_tx_ctl" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_tx_data[0]" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_tx_data[1]" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_tx_data[2]" IO_TYPE=LVCMOS33;
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IOBUF PORT "rgmii_tx_data[3]" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "eth_rx_clk" 125.0 MHz;
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FREQUENCY PORT "eth_tx_clk" 125.0 MHz;
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FREQUENCY PORT "rgmii_clocks_rx" 125.0 MHz;
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// SD card slot and level translator
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LOCATE COMP "sdcard_data[0]" SITE "N26";
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LOCATE COMP "sdcard_data[1]" SITE "N25";
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LOCATE COMP "sdcard_data[2]" SITE "N23";
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LOCATE COMP "sdcard_data[3]" SITE "N21";
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LOCATE COMP "sdcard_cmd" SITE "M24";
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LOCATE COMP "sdcard_clk" SITE "P24";
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LOCATE COMP "sdcard_cd" SITE "L22";
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LOCATE COMP "sdcard_cmd_dir" SITE "M23";
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LOCATE COMP "sdcard_dat0_dir" SITE "N24";
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LOCATE COMP "sdcard_dat13_dir" SITE "P26";
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LOCATE COMP "sdcard_vsel" SITE "L24";
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IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST;
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IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33;
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IOBUF PORT "sdcard_cmd_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_dat0_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST;
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IOBUF PORT "sdcard_dat13_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST;
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IOBUF PORT "sdcard_vsel" IO_TYPE=LVCMOS33 PULLMODE=DOWN;
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// DDR3 SDRAM
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LOCATE COMP "ddram_a[0]" SITE "T5";
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LOCATE COMP "ddram_a[1]" SITE "M3";
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LOCATE COMP "ddram_a[2]" SITE "L3";
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LOCATE COMP "ddram_a[3]" SITE "V6";
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LOCATE COMP "ddram_a[4]" SITE "K2";
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LOCATE COMP "ddram_a[5]" SITE "W6";
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LOCATE COMP "ddram_a[6]" SITE "K3";
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LOCATE COMP "ddram_a[7]" SITE "L1";
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LOCATE COMP "ddram_a[8]" SITE "H2";
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LOCATE COMP "ddram_a[9]" SITE "L2";
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LOCATE COMP "ddram_a[10]" SITE "N1";
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LOCATE COMP "ddram_a[11]" SITE "J1";
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LOCATE COMP "ddram_a[12]" SITE "M1";
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LOCATE COMP "ddram_a[13]" SITE "K1";
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LOCATE COMP "ddram_a[14]" SITE "H1";
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IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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LOCATE COMP "ddram_ba[0]" SITE "U6";
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LOCATE COMP "ddram_ba[1]" SITE "N3";
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LOCATE COMP "ddram_ba[2]" SITE "N4";
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LOCATE COMP "ddram_ras_n" SITE "T3";
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LOCATE COMP "ddram_cas_n" SITE "P2";
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LOCATE COMP "ddram_we_n" SITE "R3";
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LOCATE COMP "ddram_dm[0]" SITE "U4";
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LOCATE COMP "ddram_dm[1]" SITE "U1";
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IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_we_n" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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LOCATE COMP "ddram_dq[0]" SITE "T4";
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LOCATE COMP "ddram_dq[1]" SITE "W4";
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LOCATE COMP "ddram_dq[2]" SITE "R4";
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LOCATE COMP "ddram_dq[3]" SITE "W5";
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LOCATE COMP "ddram_dq[4]" SITE "R6";
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LOCATE COMP "ddram_dq[5]" SITE "P6";
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LOCATE COMP "ddram_dq[6]" SITE "P5";
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LOCATE COMP "ddram_dq[7]" SITE "P4";
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LOCATE COMP "ddram_dq[8]" SITE "R1";
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LOCATE COMP "ddram_dq[9]" SITE "W3";
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LOCATE COMP "ddram_dq[10]" SITE "T2";
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LOCATE COMP "ddram_dq[11]" SITE "V3";
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LOCATE COMP "ddram_dq[12]" SITE "U3";
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LOCATE COMP "ddram_dq[13]" SITE "W1";
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LOCATE COMP "ddram_dq[14]" SITE "T1";
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LOCATE COMP "ddram_dq[15]" SITE "W2";
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IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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LOCATE COMP "ddram_dqs_n[0]" SITE "U5";
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LOCATE COMP "ddram_dqs_n[1]" SITE "U2";
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LOCATE COMP "ddram_dqs_p[0]" SITE "V4";
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LOCATE COMP "ddram_dqs_p[1]" SITE "V1";
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IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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LOCATE COMP "ddram_clk_p" SITE "H3";
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LOCATE COMP "ddram_clk_n" SITE "J3";
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IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL15D_I SLEWRATE=FAST;
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IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL15D_I SLEWRATE=FAST;
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LOCATE COMP "ddram_cke" SITE "P1";
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LOCATE COMP "ddram_odt" SITE "P3";
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IOBUF PORT "ddram_cke" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_odt" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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// PMOD signals
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LOCATE COMP "pmod0_0" SITE "T25";
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IOBUF PORT "pmod0_0" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod0_1" SITE "U25";
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IOBUF PORT "pmod0_1" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod0_2" SITE "U24";
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IOBUF PORT "pmod0_2" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod0_3" SITE "V24";
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IOBUF PORT "pmod0_3" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod0_4" SITE "T26";
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IOBUF PORT "pmod0_4" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod0_5" SITE "U26";
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IOBUF PORT "pmod0_5" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod0_6" SITE "V26";
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IOBUF PORT "pmod0_6" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod0_7" SITE "W26";
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IOBUF PORT "pmod0_7" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_0" SITE "U23";
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IOBUF PORT "pmod1_0" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_1" SITE "V23";
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IOBUF PORT "pmod1_1" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_2" SITE "U22";
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IOBUF PORT "pmod1_2" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_3" SITE "V21";
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IOBUF PORT "pmod1_3" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_4" SITE "W25";
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IOBUF PORT "pmod1_4" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_5" SITE "W24";
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IOBUF PORT "pmod1_5" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_6" SITE "W23";
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IOBUF PORT "pmod1_6" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod1_7" SITE "W22";
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IOBUF PORT "pmod1_7" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_0" SITE "J24";
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IOBUF PORT "pmod2_0" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_1" SITE "H22";
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IOBUF PORT "pmod2_1" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_2" SITE "E21";
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IOBUF PORT "pmod2_2" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_3" SITE "D18";
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IOBUF PORT "pmod2_3" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_4" SITE "K22";
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IOBUF PORT "pmod2_4" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_5" SITE "J21";
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IOBUF PORT "pmod2_5" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_6" SITE "H21";
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IOBUF PORT "pmod2_6" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod2_7" SITE "D22";
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IOBUF PORT "pmod2_7" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_0" SITE "E4";
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IOBUF PORT "pmod3_0" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_1" SITE "F4";
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IOBUF PORT "pmod3_1" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_2" SITE "E6";
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IOBUF PORT "pmod3_2" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_3" SITE "H4";
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IOBUF PORT "pmod3_3" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_4" SITE "F3";
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||||
IOBUF PORT "pmod3_4" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_5" SITE "D4";
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IOBUF PORT "pmod3_5" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_6" SITE "D5";
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IOBUF PORT "pmod3_6" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod3_7" SITE "F5";
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IOBUF PORT "pmod3_7" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod4_0" SITE "E26";
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IOBUF PORT "pmod4_0" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod4_1" SITE "D25";
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IOBUF PORT "pmod4_1" IO_TYPE=LVCMOS33;
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LOCATE COMP "pmod4_2" SITE "F26";
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IOBUF PORT "pmod4_2" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod4_3" SITE "F25";
|
||||
IOBUF PORT "pmod4_3" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod4_4" SITE "C26";
|
||||
IOBUF PORT "pmod4_4" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod4_5" SITE "C25";
|
||||
IOBUF PORT "pmod4_5" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod4_6" SITE "A25";
|
||||
IOBUF PORT "pmod4_6" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod4_7" SITE "A24";
|
||||
IOBUF PORT "pmod4_7" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "pmod5_0" SITE "D19";
|
||||
IOBUF PORT "pmod5_0" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod5_1" SITE "C21";
|
||||
IOBUF PORT "pmod5_1" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod5_2" SITE "B21";
|
||||
IOBUF PORT "pmod5_2" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod5_3" SITE "C22";
|
||||
IOBUF PORT "pmod5_3" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod5_4" SITE "D21";
|
||||
IOBUF PORT "pmod5_4" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod5_5" SITE "A21";
|
||||
IOBUF PORT "pmod5_5" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod5_6" SITE "A22";
|
||||
IOBUF PORT "pmod5_6" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod5_7" SITE "A23";
|
||||
IOBUF PORT "pmod5_7" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "pmod6_0" SITE "C16";
|
||||
IOBUF PORT "pmod6_0" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod6_1" SITE "B17";
|
||||
IOBUF PORT "pmod6_1" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod6_2" SITE "C18";
|
||||
IOBUF PORT "pmod6_2" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod6_3" SITE "B19";
|
||||
IOBUF PORT "pmod6_3" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod6_4" SITE "A17";
|
||||
IOBUF PORT "pmod6_4" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod6_5" SITE "A18";
|
||||
IOBUF PORT "pmod6_5" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod6_6" SITE "A19";
|
||||
IOBUF PORT "pmod6_6" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod6_7" SITE "C19";
|
||||
IOBUF PORT "pmod6_7" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "pmod7_0" SITE "D14";
|
||||
IOBUF PORT "pmod7_0" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod7_1" SITE "B14";
|
||||
IOBUF PORT "pmod7_1" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod7_2" SITE "E14";
|
||||
IOBUF PORT "pmod7_2" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod7_3" SITE "B16";
|
||||
IOBUF PORT "pmod7_3" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod7_4" SITE "C14";
|
||||
IOBUF PORT "pmod7_4" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod7_5" SITE "A14";
|
||||
IOBUF PORT "pmod7_5" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod7_6" SITE "A15";
|
||||
IOBUF PORT "pmod7_6" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "pmod7_7" SITE "A16";
|
||||
IOBUF PORT "pmod7_7" IO_TYPE=LVCMOS33;
|
||||
@ -0,0 +1,652 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity toplevel is
|
||||
generic (
|
||||
MEMORY_SIZE : integer := 16384;
|
||||
RAM_INIT_FILE : string := "firmware.hex";
|
||||
RESET_LOW : boolean := true;
|
||||
CLK_INPUT : positive := 100000000;
|
||||
CLK_FREQUENCY : positive := 50000000;
|
||||
HAS_FPU : boolean := true;
|
||||
HAS_BTC : boolean := true;
|
||||
USE_LITEDRAM : boolean := true;
|
||||
NO_BRAM : boolean := true;
|
||||
SCLK_STARTUPE2 : boolean := false;
|
||||
SPI_FLASH_OFFSET : integer := 4194304;
|
||||
SPI_FLASH_DEF_CKDV : natural := 0;
|
||||
SPI_FLASH_DEF_QUAD : boolean := true;
|
||||
LOG_LENGTH : natural := 0;
|
||||
UART_IS_16550 : boolean := true;
|
||||
HAS_UART1 : boolean := false;
|
||||
USE_LITEETH : boolean := true;
|
||||
USE_LITESDCARD : boolean := true;
|
||||
ICACHE_NUM_LINES : natural := 64;
|
||||
NGPIO : natural := 0
|
||||
);
|
||||
port(
|
||||
ext_clk : in std_ulogic;
|
||||
ext_rst_n : in std_ulogic;
|
||||
gsrn : in std_ulogic;
|
||||
|
||||
-- UART0 signals:
|
||||
uart0_txd : out std_ulogic;
|
||||
uart0_rxd : in std_ulogic;
|
||||
|
||||
-- LEDs
|
||||
led5_r_n : out std_ulogic;
|
||||
led5_g_n : out std_ulogic;
|
||||
led5_b_n : out std_ulogic;
|
||||
led6_r_n : out std_ulogic;
|
||||
led6_g_n : out std_ulogic;
|
||||
led6_b_n : out std_ulogic;
|
||||
led7_r_n : out std_ulogic;
|
||||
led7_g_n : out std_ulogic;
|
||||
led7_b_n : out std_ulogic;
|
||||
led8_r_n : out std_ulogic;
|
||||
led8_g_n : out std_ulogic;
|
||||
led8_b_n : out std_ulogic;
|
||||
|
||||
-- SPI
|
||||
spi_flash_cs_n : out std_ulogic;
|
||||
spi_flash_mosi : inout std_ulogic;
|
||||
spi_flash_miso : inout std_ulogic;
|
||||
spi_flash_wp_n : inout std_ulogic;
|
||||
spi_flash_hold_n : inout std_ulogic;
|
||||
|
||||
-- Ethernet
|
||||
rgmii_clocks_rx : in std_ulogic;
|
||||
rgmii_clocks_tx : out std_ulogic;
|
||||
rgmii_rst_n : out std_ulogic;
|
||||
rgmii_int_n : in std_ulogic;
|
||||
rgmii_mdc : out std_ulogic;
|
||||
rgmii_mdio : inout std_ulogic;
|
||||
rgmii_rx_ctl : in std_ulogic;
|
||||
rgmii_rx_data : in std_ulogic_vector(3 downto 0);
|
||||
rgmii_tx_ctl : out std_ulogic;
|
||||
rgmii_tx_data : out std_ulogic_vector(3 downto 0);
|
||||
|
||||
-- SD card wires
|
||||
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
||||
sdcard_cmd : inout std_ulogic;
|
||||
sdcard_clk : out std_ulogic;
|
||||
sdcard_cd : in std_ulogic;
|
||||
sdcard_cmd_dir : out std_ulogic;
|
||||
sdcard_dat0_dir : out std_ulogic;
|
||||
sdcard_dat13_dir : out std_ulogic;
|
||||
sdcard_vsel : out std_ulogic;
|
||||
|
||||
-- PMOD ports 0 - 7
|
||||
pmod0_0 : inout std_ulogic;
|
||||
pmod0_1 : inout std_ulogic;
|
||||
pmod0_2 : inout std_ulogic;
|
||||
pmod0_3 : inout std_ulogic;
|
||||
pmod0_4 : inout std_ulogic;
|
||||
pmod0_5 : inout std_ulogic;
|
||||
pmod0_6 : inout std_ulogic;
|
||||
pmod0_7 : inout std_ulogic;
|
||||
pmod1_0 : inout std_ulogic;
|
||||
pmod1_1 : inout std_ulogic;
|
||||
pmod1_2 : inout std_ulogic;
|
||||
pmod1_3 : inout std_ulogic;
|
||||
pmod1_4 : inout std_ulogic;
|
||||
pmod1_5 : inout std_ulogic;
|
||||
pmod1_6 : inout std_ulogic;
|
||||
pmod1_7 : inout std_ulogic;
|
||||
pmod2_0 : inout std_ulogic;
|
||||
pmod2_1 : inout std_ulogic;
|
||||
pmod2_2 : inout std_ulogic;
|
||||
pmod2_3 : inout std_ulogic;
|
||||
pmod2_4 : inout std_ulogic;
|
||||
pmod2_5 : inout std_ulogic;
|
||||
pmod2_6 : inout std_ulogic;
|
||||
pmod2_7 : inout std_ulogic;
|
||||
pmod3_0 : inout std_ulogic;
|
||||
pmod3_1 : inout std_ulogic;
|
||||
pmod3_2 : inout std_ulogic;
|
||||
pmod3_3 : inout std_ulogic;
|
||||
pmod3_4 : inout std_ulogic;
|
||||
pmod3_5 : inout std_ulogic;
|
||||
pmod3_6 : inout std_ulogic;
|
||||
pmod3_7 : inout std_ulogic;
|
||||
pmod4_0 : inout std_ulogic; -- 0n
|
||||
pmod4_1 : inout std_ulogic; -- 0p
|
||||
pmod4_2 : inout std_ulogic; -- 1n
|
||||
pmod4_3 : inout std_ulogic; -- 1p
|
||||
pmod4_4 : inout std_ulogic; -- 2n
|
||||
pmod4_5 : inout std_ulogic; -- 2p
|
||||
pmod4_6 : inout std_ulogic; -- 3n
|
||||
pmod4_7 : inout std_ulogic; -- 3p
|
||||
pmod5_0 : inout std_ulogic;
|
||||
pmod5_1 : inout std_ulogic;
|
||||
pmod5_2 : inout std_ulogic;
|
||||
pmod5_3 : inout std_ulogic;
|
||||
pmod5_4 : inout std_ulogic;
|
||||
pmod5_5 : inout std_ulogic;
|
||||
pmod5_6 : inout std_ulogic;
|
||||
pmod5_7 : inout std_ulogic;
|
||||
pmod6_0 : inout std_ulogic;
|
||||
pmod6_1 : inout std_ulogic;
|
||||
pmod6_2 : inout std_ulogic;
|
||||
pmod6_3 : inout std_ulogic;
|
||||
pmod6_4 : inout std_ulogic;
|
||||
pmod6_5 : inout std_ulogic;
|
||||
pmod6_6 : inout std_ulogic;
|
||||
pmod6_7 : inout std_ulogic;
|
||||
pmod7_0 : inout std_ulogic;
|
||||
pmod7_1 : inout std_ulogic;
|
||||
pmod7_2 : inout std_ulogic;
|
||||
pmod7_3 : inout std_ulogic;
|
||||
pmod7_4 : inout std_ulogic;
|
||||
pmod7_5 : inout std_ulogic;
|
||||
pmod7_6 : inout std_ulogic;
|
||||
pmod7_7 : inout std_ulogic;
|
||||
|
||||
-- DRAM wires
|
||||
ddram_a : out std_ulogic_vector(14 downto 0);
|
||||
ddram_ba : out std_ulogic_vector(2 downto 0);
|
||||
ddram_ras_n : out std_ulogic;
|
||||
ddram_cas_n : out std_ulogic;
|
||||
ddram_we_n : out std_ulogic;
|
||||
ddram_dm : out std_ulogic_vector(1 downto 0);
|
||||
ddram_dq : inout std_ulogic_vector(15 downto 0);
|
||||
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_clk_p : out std_ulogic_vector(0 downto 0);
|
||||
-- only the positive differential pin is instantiated
|
||||
--ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
|
||||
--ddram_clk_n : out std_ulogic_vector(0 downto 0);
|
||||
ddram_cke : out std_ulogic;
|
||||
ddram_odt : out std_ulogic
|
||||
);
|
||||
end entity toplevel;
|
||||
|
||||
architecture behaviour of toplevel is
|
||||
|
||||
-- Reset signals:
|
||||
signal soc_rst : std_ulogic;
|
||||
signal pll_rst : std_ulogic;
|
||||
|
||||
-- Internal clock signals:
|
||||
signal system_clk : std_ulogic;
|
||||
signal system_clk_locked : std_ulogic;
|
||||
|
||||
-- External IOs from the SoC
|
||||
signal wb_ext_io_in : wb_io_master_out;
|
||||
signal wb_ext_io_out : wb_io_slave_out;
|
||||
signal wb_ext_is_dram_csr : std_ulogic;
|
||||
signal wb_ext_is_dram_init : std_ulogic;
|
||||
signal wb_ext_is_eth : std_ulogic;
|
||||
signal wb_ext_is_sdcard : std_ulogic;
|
||||
|
||||
-- DRAM main data wishbone connection
|
||||
signal wb_dram_in : wishbone_master_out;
|
||||
signal wb_dram_out : wishbone_slave_out;
|
||||
|
||||
-- DRAM control wishbone connection
|
||||
signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
|
||||
-- LiteEth connection
|
||||
signal ext_irq_eth : std_ulogic;
|
||||
signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
|
||||
-- LiteSDCard connection
|
||||
signal ext_irq_sdcard : std_ulogic := '0';
|
||||
signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
|
||||
signal wb_sddma_in : wb_io_slave_out;
|
||||
signal wb_sddma_nr : wb_io_master_out;
|
||||
signal wb_sddma_ir : wb_io_slave_out;
|
||||
-- for conversion from non-pipelined wishbone to pipelined
|
||||
signal wb_sddma_stb_sent : std_ulogic;
|
||||
|
||||
-- SPI flash
|
||||
signal spi_sck : std_ulogic;
|
||||
signal spi_sck_ts : std_ulogic;
|
||||
signal spi_cs_n : std_ulogic;
|
||||
signal spi_sdat_o : std_ulogic_vector(3 downto 0);
|
||||
signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
|
||||
signal spi_sdat_i : std_ulogic_vector(3 downto 0);
|
||||
|
||||
-- Fixup various memory sizes based on generics
|
||||
function get_bram_size return natural is
|
||||
begin
|
||||
if USE_LITEDRAM and NO_BRAM then
|
||||
return 0;
|
||||
else
|
||||
return MEMORY_SIZE;
|
||||
end if;
|
||||
end function;
|
||||
|
||||
function get_payload_size return natural is
|
||||
begin
|
||||
if USE_LITEDRAM and NO_BRAM then
|
||||
return MEMORY_SIZE;
|
||||
else
|
||||
return 0;
|
||||
end if;
|
||||
end function;
|
||||
|
||||
constant BRAM_SIZE : natural := get_bram_size;
|
||||
constant PAYLOAD_SIZE : natural := get_payload_size;
|
||||
|
||||
COMPONENT USRMCLK
|
||||
PORT(
|
||||
USRMCLKI : IN STD_ULOGIC;
|
||||
USRMCLKTS : IN STD_ULOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
attribute syn_noprune: boolean ;
|
||||
attribute syn_noprune of USRMCLK: component is true;
|
||||
|
||||
begin
|
||||
|
||||
-- Main SoC
|
||||
soc0: entity work.soc
|
||||
generic map(
|
||||
MEMORY_SIZE => BRAM_SIZE,
|
||||
RAM_INIT_FILE => RAM_INIT_FILE,
|
||||
SIM => false,
|
||||
CLK_FREQ => CLK_FREQUENCY,
|
||||
HAS_FPU => HAS_FPU,
|
||||
HAS_BTC => HAS_BTC,
|
||||
HAS_DRAM => USE_LITEDRAM,
|
||||
DRAM_SIZE => 512 * 1024 * 1024,
|
||||
DRAM_INIT_SIZE => PAYLOAD_SIZE,
|
||||
HAS_SPI_FLASH => true,
|
||||
SPI_FLASH_DLINES => 4,
|
||||
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
|
||||
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
|
||||
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
|
||||
LOG_LENGTH => LOG_LENGTH,
|
||||
UART0_IS_16550 => UART_IS_16550,
|
||||
HAS_UART1 => HAS_UART1,
|
||||
HAS_LITEETH => USE_LITEETH,
|
||||
HAS_SD_CARD => USE_LITESDCARD,
|
||||
ICACHE_NUM_LINES => ICACHE_NUM_LINES,
|
||||
NGPIO => NGPIO
|
||||
)
|
||||
port map (
|
||||
-- System signals
|
||||
system_clk => system_clk,
|
||||
rst => soc_rst,
|
||||
|
||||
-- UART signals
|
||||
uart0_txd => uart0_txd,
|
||||
uart0_rxd => uart0_rxd,
|
||||
|
||||
-- SPI signals
|
||||
spi_flash_sck => spi_sck,
|
||||
spi_flash_cs_n => spi_cs_n,
|
||||
spi_flash_sdat_o => spi_sdat_o,
|
||||
spi_flash_sdat_oe => spi_sdat_oe,
|
||||
spi_flash_sdat_i => spi_sdat_i,
|
||||
|
||||
-- External interrupts
|
||||
ext_irq_eth => ext_irq_eth,
|
||||
ext_irq_sdcard => ext_irq_sdcard,
|
||||
|
||||
-- DRAM wishbone
|
||||
wb_dram_in => wb_dram_in,
|
||||
wb_dram_out => wb_dram_out,
|
||||
|
||||
-- IO wishbone
|
||||
wb_ext_io_in => wb_ext_io_in,
|
||||
wb_ext_io_out => wb_ext_io_out,
|
||||
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
|
||||
wb_ext_is_dram_init => wb_ext_is_dram_init,
|
||||
wb_ext_is_eth => wb_ext_is_eth,
|
||||
wb_ext_is_sdcard => wb_ext_is_sdcard,
|
||||
|
||||
-- DMA wishbone
|
||||
wishbone_dma_in => wb_sddma_in,
|
||||
wishbone_dma_out => wb_sddma_out
|
||||
);
|
||||
|
||||
-- SPI Flash
|
||||
--
|
||||
spi_flash_cs_n <= spi_cs_n;
|
||||
spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
|
||||
spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
|
||||
spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
|
||||
spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
|
||||
spi_sdat_i(0) <= spi_flash_mosi;
|
||||
spi_sdat_i(1) <= spi_flash_miso;
|
||||
spi_sdat_i(2) <= spi_flash_wp_n;
|
||||
spi_sdat_i(3) <= spi_flash_hold_n;
|
||||
spi_sck_ts <= '0';
|
||||
|
||||
uclk: USRMCLK port map (
|
||||
USRMCLKI => spi_sck,
|
||||
USRMCLKTS => spi_sck_ts
|
||||
);
|
||||
|
||||
nodram: if not USE_LITEDRAM generate
|
||||
signal div2 : std_ulogic := '0';
|
||||
begin
|
||||
reset_controller: entity work.soc_reset
|
||||
generic map(
|
||||
RESET_LOW => RESET_LOW
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_clk => system_clk,
|
||||
pll_locked_in => system_clk_locked,
|
||||
ext_rst_in => ext_rst_n and gsrn,
|
||||
pll_rst_out => pll_rst,
|
||||
rst_out => soc_rst
|
||||
);
|
||||
|
||||
process(ext_clk)
|
||||
begin
|
||||
if rising_edge(ext_clk) then
|
||||
div2 <= not div2;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
system_clk <= div2;
|
||||
system_clk_locked <= '1';
|
||||
|
||||
led8_r_n <= '1';
|
||||
led8_g_n <= '1';
|
||||
led8_b_n <= '1';
|
||||
|
||||
end generate;
|
||||
|
||||
has_dram: if USE_LITEDRAM generate
|
||||
signal dram_init_done : std_ulogic;
|
||||
signal dram_init_error : std_ulogic;
|
||||
signal dram_sys_rst : std_ulogic;
|
||||
begin
|
||||
|
||||
-- Eventually dig out the frequency from
|
||||
-- litesdram generate.py sys_clk_freq
|
||||
-- but for now, assert it's 50Mhz for ECPIX-5
|
||||
assert CLK_FREQUENCY = 50000000;
|
||||
|
||||
reset_controller: entity work.soc_reset
|
||||
generic map(
|
||||
RESET_LOW => RESET_LOW,
|
||||
PLL_RESET_BITS => 18,
|
||||
SOC_RESET_BITS => 20
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_clk => system_clk,
|
||||
pll_locked_in => system_clk_locked and not dram_sys_rst,
|
||||
ext_rst_in => ext_rst_n and gsrn,
|
||||
pll_rst_out => pll_rst,
|
||||
rst_out => soc_rst
|
||||
);
|
||||
|
||||
-- Generate SoC reset
|
||||
soc_rst_gen: process(system_clk)
|
||||
begin
|
||||
if ext_rst_n = '0' then
|
||||
soc_rst <= '1';
|
||||
elsif rising_edge(system_clk) then
|
||||
soc_rst <= dram_sys_rst or not system_clk_locked;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dram: entity work.litedram_wrapper
|
||||
generic map(
|
||||
DRAM_ABITS => 25,
|
||||
DRAM_ALINES => 15,
|
||||
DRAM_DLINES => 16,
|
||||
DRAM_CKLINES => 1,
|
||||
DRAM_PORT_WIDTH => 128,
|
||||
PAYLOAD_FILE => RAM_INIT_FILE,
|
||||
PAYLOAD_SIZE => PAYLOAD_SIZE
|
||||
)
|
||||
port map(
|
||||
clk_in => ext_clk,
|
||||
rst => pll_rst,
|
||||
system_clk => system_clk,
|
||||
system_reset => dram_sys_rst,
|
||||
pll_locked => system_clk_locked,
|
||||
|
||||
wb_in => wb_dram_in,
|
||||
wb_out => wb_dram_out,
|
||||
wb_ctrl_in => wb_ext_io_in,
|
||||
wb_ctrl_out => wb_dram_ctrl_out,
|
||||
wb_ctrl_is_csr => wb_ext_is_dram_csr,
|
||||
wb_ctrl_is_init => wb_ext_is_dram_init,
|
||||
|
||||
init_done => dram_init_done,
|
||||
init_error => dram_init_error,
|
||||
|
||||
ddram_a => ddram_a,
|
||||
ddram_ba => ddram_ba,
|
||||
ddram_ras_n => ddram_ras_n,
|
||||
ddram_cas_n => ddram_cas_n,
|
||||
ddram_we_n => ddram_we_n,
|
||||
ddram_dm => ddram_dm,
|
||||
ddram_dq => ddram_dq,
|
||||
ddram_dqs_p => ddram_dqs_p,
|
||||
ddram_clk_p => ddram_clk_p,
|
||||
-- only the positive differential pin is instantiated
|
||||
--ddram_dqs_n => ddram_dqs_n,
|
||||
--ddram_clk_n => ddram_clk_n,
|
||||
ddram_cke => ddram_cke,
|
||||
ddram_odt => ddram_odt
|
||||
);
|
||||
|
||||
-- active-low outputs to the LED
|
||||
led8_b_n <= dram_init_done;
|
||||
led8_r_n <= not dram_init_error;
|
||||
led8_g_n <= not (dram_init_done and not dram_init_error);
|
||||
end generate;
|
||||
|
||||
has_liteeth : if USE_LITEETH generate
|
||||
|
||||
component liteeth_core port (
|
||||
sys_clock : in std_ulogic;
|
||||
sys_reset : in std_ulogic;
|
||||
rgmii_clocks_tx : out std_ulogic;
|
||||
rgmii_clocks_rx : in std_ulogic;
|
||||
rgmii_rst_n : out std_ulogic;
|
||||
rgmii_int_n : in std_ulogic;
|
||||
rgmii_mdio : inout std_ulogic;
|
||||
rgmii_mdc : out std_ulogic;
|
||||
rgmii_rx_ctl : in std_ulogic;
|
||||
rgmii_rx_data : in std_ulogic_vector(3 downto 0);
|
||||
rgmii_tx_ctl : out std_ulogic;
|
||||
rgmii_tx_data : out std_ulogic_vector(3 downto 0);
|
||||
wishbone_adr : in std_ulogic_vector(29 downto 0);
|
||||
wishbone_dat_w : in std_ulogic_vector(31 downto 0);
|
||||
wishbone_dat_r : out std_ulogic_vector(31 downto 0);
|
||||
wishbone_sel : in std_ulogic_vector(3 downto 0);
|
||||
wishbone_cyc : in std_ulogic;
|
||||
wishbone_stb : in std_ulogic;
|
||||
wishbone_ack : out std_ulogic;
|
||||
wishbone_we : in std_ulogic;
|
||||
wishbone_cti : in std_ulogic_vector(2 downto 0);
|
||||
wishbone_bte : in std_ulogic_vector(1 downto 0);
|
||||
wishbone_err : out std_ulogic;
|
||||
interrupt : out std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal wb_eth_cyc : std_ulogic;
|
||||
signal wb_eth_adr : std_ulogic_vector(29 downto 0);
|
||||
|
||||
begin
|
||||
liteeth : liteeth_core
|
||||
port map(
|
||||
sys_clock => system_clk,
|
||||
sys_reset => soc_rst,
|
||||
rgmii_clocks_tx => rgmii_clocks_tx,
|
||||
rgmii_clocks_rx => rgmii_clocks_rx,
|
||||
rgmii_rst_n => rgmii_rst_n,
|
||||
rgmii_int_n => rgmii_int_n,
|
||||
rgmii_mdio => rgmii_mdio,
|
||||
rgmii_mdc => rgmii_mdc,
|
||||
rgmii_rx_ctl => rgmii_rx_ctl,
|
||||
rgmii_rx_data => rgmii_rx_data,
|
||||
rgmii_tx_ctl => rgmii_tx_ctl,
|
||||
rgmii_tx_data => rgmii_tx_data,
|
||||
wishbone_adr => wb_eth_adr,
|
||||
wishbone_dat_w => wb_ext_io_in.dat,
|
||||
wishbone_dat_r => wb_eth_out.dat,
|
||||
wishbone_sel => wb_ext_io_in.sel,
|
||||
wishbone_cyc => wb_eth_cyc,
|
||||
wishbone_stb => wb_ext_io_in.stb,
|
||||
wishbone_ack => wb_eth_out.ack,
|
||||
wishbone_we => wb_ext_io_in.we,
|
||||
wishbone_cti => "000",
|
||||
wishbone_bte => "00",
|
||||
wishbone_err => open,
|
||||
interrupt => ext_irq_eth
|
||||
);
|
||||
|
||||
-- Gate cyc with "chip select" from soc
|
||||
wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
|
||||
|
||||
-- Remove top address bits as liteeth decoder doesn't know about them
|
||||
wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0);
|
||||
|
||||
-- LiteETH isn't pipelined
|
||||
wb_eth_out.stall <= not wb_eth_out.ack;
|
||||
|
||||
end generate;
|
||||
|
||||
no_liteeth : if not USE_LITEETH generate
|
||||
ext_irq_eth <= '0';
|
||||
end generate;
|
||||
|
||||
-- SD card
|
||||
-- The ECPIX-5 has a buffer/level translator chip in order to be able to
|
||||
-- support 1.8V signalling to the SD card as well as 3V signalling.
|
||||
-- Litesdcard doesn't currently support voltage selection, or the higher
|
||||
-- data transfer rates that require the lower voltage.
|
||||
has_sdcard : if USE_LITESDCARD generate
|
||||
component litesdcard_core port (
|
||||
clk : in std_ulogic;
|
||||
rst : in std_ulogic;
|
||||
irq : out std_ulogic;
|
||||
-- wishbone for accessing control registers
|
||||
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
|
||||
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
|
||||
wb_ctrl_cyc : in std_ulogic;
|
||||
wb_ctrl_stb : in std_ulogic;
|
||||
wb_ctrl_ack : out std_ulogic;
|
||||
wb_ctrl_we : in std_ulogic;
|
||||
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
|
||||
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
|
||||
wb_ctrl_err : out std_ulogic;
|
||||
-- wishbone for SD card core to use for DMA
|
||||
wb_dma_adr : out std_ulogic_vector(29 downto 0);
|
||||
wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
|
||||
wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
|
||||
wb_dma_sel : out std_ulogic_vector(3 downto 0);
|
||||
wb_dma_cyc : out std_ulogic;
|
||||
wb_dma_stb : out std_ulogic;
|
||||
wb_dma_ack : in std_ulogic;
|
||||
wb_dma_we : out std_ulogic;
|
||||
wb_dma_cti : out std_ulogic_vector(2 downto 0);
|
||||
wb_dma_bte : out std_ulogic_vector(1 downto 0);
|
||||
wb_dma_err : in std_ulogic;
|
||||
-- connections to SD card
|
||||
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
||||
sdcard_cmd : inout std_ulogic;
|
||||
sdcard_clk : out std_ulogic;
|
||||
sdcard_cd : in std_ulogic;
|
||||
sdcard_cmd_dir : out std_ulogic;
|
||||
sdcard_dat0_dir : out std_ulogic;
|
||||
sdcard_dat13_dir : out std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal wb_sdcard_cyc : std_ulogic;
|
||||
signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
|
||||
|
||||
begin
|
||||
litesdcard : litesdcard_core
|
||||
port map (
|
||||
clk => system_clk,
|
||||
rst => soc_rst,
|
||||
irq => ext_irq_sdcard,
|
||||
wb_ctrl_adr => wb_sdcard_adr,
|
||||
wb_ctrl_dat_w => wb_ext_io_in.dat,
|
||||
wb_ctrl_dat_r => wb_sdcard_out.dat,
|
||||
wb_ctrl_sel => wb_ext_io_in.sel,
|
||||
wb_ctrl_cyc => wb_sdcard_cyc,
|
||||
wb_ctrl_stb => wb_ext_io_in.stb,
|
||||
wb_ctrl_ack => wb_sdcard_out.ack,
|
||||
wb_ctrl_we => wb_ext_io_in.we,
|
||||
wb_ctrl_cti => "000",
|
||||
wb_ctrl_bte => "00",
|
||||
wb_ctrl_err => open,
|
||||
wb_dma_adr => wb_sddma_nr.adr,
|
||||
wb_dma_dat_w => wb_sddma_nr.dat,
|
||||
wb_dma_dat_r => wb_sddma_ir.dat,
|
||||
wb_dma_sel => wb_sddma_nr.sel,
|
||||
wb_dma_cyc => wb_sddma_nr.cyc,
|
||||
wb_dma_stb => wb_sddma_nr.stb,
|
||||
wb_dma_ack => wb_sddma_ir.ack,
|
||||
wb_dma_we => wb_sddma_nr.we,
|
||||
wb_dma_cti => open,
|
||||
wb_dma_bte => open,
|
||||
wb_dma_err => '0',
|
||||
sdcard_data => sdcard_data,
|
||||
sdcard_cmd => sdcard_cmd,
|
||||
sdcard_clk => sdcard_clk,
|
||||
sdcard_cd => sdcard_cd,
|
||||
sdcard_cmd_dir => sdcard_cmd_dir,
|
||||
sdcard_dat0_dir => sdcard_dat0_dir,
|
||||
sdcard_dat13_dir => sdcard_dat13_dir
|
||||
);
|
||||
|
||||
-- Select 3V signalling
|
||||
sdcard_vsel <= '0';
|
||||
|
||||
-- Gate cyc with chip select from SoC
|
||||
wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
|
||||
|
||||
wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
|
||||
|
||||
wb_sdcard_out.stall <= not wb_sdcard_out.ack;
|
||||
|
||||
-- Convert non-pipelined DMA wishbone to pipelined by suppressing
|
||||
-- non-acknowledged strobes
|
||||
process(system_clk)
|
||||
begin
|
||||
if rising_edge(system_clk) then
|
||||
wb_sddma_out <= wb_sddma_nr;
|
||||
if wb_sddma_stb_sent = '1' or
|
||||
(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
|
||||
wb_sddma_out.stb <= '0';
|
||||
end if;
|
||||
if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
|
||||
wb_sddma_stb_sent <= '0';
|
||||
elsif wb_sddma_in.stall = '0' then
|
||||
wb_sddma_stb_sent <= wb_sddma_nr.stb;
|
||||
end if;
|
||||
wb_sddma_ir <= wb_sddma_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end generate;
|
||||
|
||||
-- Mux WB response on the IO bus
|
||||
wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
|
||||
wb_sdcard_out when wb_ext_is_sdcard = '1' else
|
||||
wb_dram_ctrl_out;
|
||||
|
||||
led5_r_n <= '1';
|
||||
led5_g_n <= '1';
|
||||
led5_b_n <= '1';
|
||||
led6_r_n <= '1';
|
||||
led6_g_n <= '1';
|
||||
led6_b_n <= '1';
|
||||
led7_r_n <= not soc_rst;
|
||||
led7_g_n <= not system_clk_locked;
|
||||
led7_b_n <= '1';
|
||||
|
||||
end architecture behaviour;
|
||||
@ -0,0 +1,34 @@
|
||||
# Based on orangecrab-85-0.2.yml and arty.yml
|
||||
|
||||
{
|
||||
"cpu": "None", # CPU type (ex vexriscv, serv, None)
|
||||
"device": "LFE5UM5G-85F-8BG554I",
|
||||
"memtype": "DDR3", # DRAM type
|
||||
|
||||
"cmd_latency": 0,
|
||||
"sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM
|
||||
"sdram_module_nb": 2, # Number of byte groups
|
||||
"sdram_rank_nb": 1, # Number of ranks
|
||||
"sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY
|
||||
|
||||
# Electrical ---------------------------------------------------------------
|
||||
"rtt_nom": "60ohm", # Nominal termination. (Default)
|
||||
"rtt_wr": "60ohm", # Write termination. (Default)
|
||||
"ron": "34ohm", # Output driver impedance. (Default)
|
||||
|
||||
# Frequency ----------------------------------------------------------------
|
||||
"input_clk_freq": 100e6, # Input clock frequency
|
||||
"sys_clk_freq": 50e6, # System clock frequency (DDR_clk = 4 x sys_clk)
|
||||
"init_clk_freq": 50e6, # ?
|
||||
|
||||
# Core ---------------------------------------------------------------------
|
||||
"cmd_buffer_depth": 16, # Depth of the command buffer
|
||||
|
||||
# User Ports ---------------------------------------------------------------
|
||||
"user_ports": {
|
||||
"native_0": {
|
||||
"type": "native",
|
||||
"block_until_ready": False,
|
||||
},
|
||||
},
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -0,0 +1,123 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
use work.utils.all;
|
||||
|
||||
entity dram_init_mem is
|
||||
generic (
|
||||
EXTRA_PAYLOAD_FILE : string := "";
|
||||
EXTRA_PAYLOAD_SIZE : integer := 0
|
||||
);
|
||||
port (
|
||||
clk : in std_ulogic;
|
||||
wb_in : in wb_io_master_out;
|
||||
wb_out : out wb_io_slave_out
|
||||
);
|
||||
end entity dram_init_mem;
|
||||
|
||||
architecture rtl of dram_init_mem is
|
||||
|
||||
constant INIT_RAM_SIZE : integer := 24576;
|
||||
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
|
||||
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
|
||||
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
|
||||
constant INIT_RAM_FILE : string := "litedram_core.init";
|
||||
|
||||
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
|
||||
|
||||
-- XXX FIXME: Have a single init function called twice with
|
||||
-- an offset as argument
|
||||
procedure init_load_payload(ram: inout ram_t; filename: string) is
|
||||
file payload_file : text open read_mode is filename;
|
||||
variable ram_line : line;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
begin
|
||||
for i in 0 to RND_PAYLOAD_SIZE-1 loop
|
||||
exit when endfile(payload_file);
|
||||
readline(payload_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
|
||||
ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
assert endfile(payload_file) report "Payload too big !" severity failure;
|
||||
end procedure;
|
||||
|
||||
impure function init_load_ram(name : string) return ram_t is
|
||||
file ram_file : text open read_mode is name;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
variable ram_line : line;
|
||||
begin
|
||||
report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
|
||||
" rounded to:" & integer'image(RND_PAYLOAD_SIZE);
|
||||
report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
|
||||
" bytes using " & integer'image(INIT_RAM_ABITS) &
|
||||
" address bits";
|
||||
for i in 0 to (INIT_RAM_SIZE/8)-1 loop
|
||||
exit when endfile(ram_file);
|
||||
readline(ram_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
temp_ram(i*2) := temp_word(31 downto 0);
|
||||
temp_ram(i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
if RND_PAYLOAD_SIZE /= 0 then
|
||||
init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
|
||||
end if;
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function init_zero return ram_t is
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
begin
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function initialize_ram(filename: string) return ram_t is
|
||||
begin
|
||||
report "Opening file " & filename;
|
||||
if filename'length = 0 then
|
||||
return init_zero;
|
||||
else
|
||||
return init_load_ram(filename);
|
||||
end if;
|
||||
end function;
|
||||
signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
|
||||
|
||||
attribute ram_style : string;
|
||||
attribute ram_style of init_ram: signal is "block";
|
||||
|
||||
signal obuf : std_ulogic_vector(31 downto 0);
|
||||
signal oack : std_ulogic;
|
||||
begin
|
||||
|
||||
init_ram_0: process(clk)
|
||||
variable adr : integer;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
oack <= '0';
|
||||
if (wb_in.cyc and wb_in.stb) = '1' then
|
||||
adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
|
||||
if wb_in.we = '0' then
|
||||
obuf <= init_ram(adr);
|
||||
else
|
||||
for i in 0 to 3 loop
|
||||
if wb_in.sel(i) = '1' then
|
||||
init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
|
||||
wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
oack <= '1';
|
||||
end if;
|
||||
wb_out.ack <= oack;
|
||||
wb_out.dat <= obuf;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
wb_out.stall <= '0';
|
||||
|
||||
end architecture rtl;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -0,0 +1,18 @@
|
||||
# This file is derived from nexys_video.yml, which is:
|
||||
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# License: BSD
|
||||
|
||||
# PHY ----------------------------------------------------------------------
|
||||
phy: LiteEthECP5PHYRGMII
|
||||
vendor: lattice
|
||||
# Core ---------------------------------------------------------------------
|
||||
clk_freq: 125e6
|
||||
core: wishbone
|
||||
endianness: little
|
||||
ntxslots: 2
|
||||
nrxslots: 2
|
||||
phy_rx_delay: 0
|
||||
|
||||
soc:
|
||||
mem_map:
|
||||
ethmac: 0x00010000
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,6 @@
|
||||
adapter driver ftdi
|
||||
ftdi vid_pid 0x0403 0x6011
|
||||
ftdi channel 0
|
||||
ftdi layout_init 0xfff8 0xfffb
|
||||
reset_config none
|
||||
adapter speed 25000
|
||||
Loading…
Reference in New Issue