cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity

Reformat helpers

Browse Source 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/66/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 9ff86a62f5
commit ae42370d24
1 changed files with 191 additions and 191 deletions
Show Stats Download Patch File Download Diff File

382
helpers.vhdl
Unescape Escape View File

@ -5,205 +5,205 @@ use ieee.numeric_std.all;
library work; library work;


package helpers is package helpers is
function fls_32 (val: std_ulogic_vector(31 downto 0)) return integer; function fls_32 (val: std_ulogic_vector(31 downto 0)) return integer;
function ffs_32 (val: std_ulogic_vector(31 downto 0)) return integer; function ffs_32 (val: std_ulogic_vector(31 downto 0)) return integer;


function fls_64 (val: std_ulogic_vector(63 downto 0)) return integer; function fls_64 (val: std_ulogic_vector(63 downto 0)) return integer;
function ffs_64 (val: std_ulogic_vector(63 downto 0)) return integer; function ffs_64 (val: std_ulogic_vector(63 downto 0)) return integer;


function popcnt8(val: std_ulogic_vector(7 downto 0)) return std_ulogic_vector; function popcnt8(val: std_ulogic_vector(7 downto 0)) return std_ulogic_vector;
function popcnt32(val: std_ulogic_vector(31 downto 0)) return std_ulogic_vector; function popcnt32(val: std_ulogic_vector(31 downto 0)) return std_ulogic_vector;
function popcnt64(val: std_ulogic_vector(63 downto 0)) return std_ulogic_vector; function popcnt64(val: std_ulogic_vector(63 downto 0)) return std_ulogic_vector;


function cmp_one_byte(a, b: std_ulogic_vector(7 downto 0)) return std_ulogic_vector; function cmp_one_byte(a, b: std_ulogic_vector(7 downto 0)) return std_ulogic_vector;


function ppc_signed_compare(a, b: signed(63 downto 0)) return std_ulogic_vector; function ppc_signed_compare(a, b: signed(63 downto 0)) return std_ulogic_vector;
function ppc_unsigned_compare(a, b: unsigned(63 downto 0)) return std_ulogic_vector; function ppc_unsigned_compare(a, b: unsigned(63 downto 0)) return std_ulogic_vector;


function ra_or_zero(ra: std_ulogic_vector(63 downto 0); reg: std_ulogic_vector(4 downto 0)) return std_ulogic_vector; function ra_or_zero(ra: std_ulogic_vector(63 downto 0); reg: std_ulogic_vector(4 downto 0)) return std_ulogic_vector;


function byte_reverse(val: std_ulogic_vector(63 downto 0); size: integer) return std_ulogic_vector; function byte_reverse(val: std_ulogic_vector(63 downto 0); size: integer) return std_ulogic_vector;


function sign_extend(val: std_ulogic_vector(63 downto 0); size: natural) return std_ulogic_vector; function sign_extend(val: std_ulogic_vector(63 downto 0); size: natural) return std_ulogic_vector;
end package helpers; end package helpers;


package body helpers is package body helpers is
function fls_32 (val: std_ulogic_vector(31 downto 0)) return integer is function fls_32 (val: std_ulogic_vector(31 downto 0)) return integer is
variable ret: integer; variable ret: integer;
begin begin
ret := 32; ret := 32;
for i in val'range loop for i in val'range loop
if val(i) = '1' then if val(i) = '1' then
ret := 31 - i; ret := 31 - i;
exit; exit;
end if; end if;
end loop; end loop;


return ret; return ret;
end; end;


function ffs_32 (val: std_ulogic_vector(31 downto 0)) return integer is function ffs_32 (val: std_ulogic_vector(31 downto 0)) return integer is
variable ret: integer; variable ret: integer;
begin begin
ret := 32; ret := 32;
for i in val'reverse_range loop for i in val'reverse_range loop
if val(i) = '1' then if val(i) = '1' then
ret := i; ret := i;
exit; exit;
end if; end if;
end loop; end loop;


return ret; return ret;
end; end;


function fls_64 (val: std_ulogic_vector(63 downto 0)) return integer is function fls_64 (val: std_ulogic_vector(63 downto 0)) return integer is
variable ret: integer; variable ret: integer;
begin begin
ret := 64; ret := 64;
for i in val'range loop for i in val'range loop
if val(i) = '1' then if val(i) = '1' then
ret := 63 - i; ret := 63 - i;
exit; exit;
end if; end if;
end loop; end loop;


return ret; return ret;
end; end;


function ffs_64 (val: std_ulogic_vector(63 downto 0)) return integer is function ffs_64 (val: std_ulogic_vector(63 downto 0)) return integer is
variable ret: integer; variable ret: integer;
begin begin
ret := 64; ret := 64;
for i in val'reverse_range loop for i in val'reverse_range loop
if val(i) = '1' then if val(i) = '1' then
ret := i; ret := i;
exit; exit;
end if; end if;
end loop; end loop;


return ret; return ret;
end; end;


function popcnt8(val: std_ulogic_vector(7 downto 0)) return std_ulogic_vector is function popcnt8(val: std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
variable ret: unsigned(3 downto 0) := (others => '0'); variable ret: unsigned(3 downto 0) := (others => '0');
begin begin
for i in val'range loop for i in val'range loop
ret := ret + ("000" & val(i)); ret := ret + ("000" & val(i));
end loop; end loop;


return std_ulogic_vector(resize(ret, val'length)); return std_ulogic_vector(resize(ret, val'length));
end; end;


function popcnt32(val: std_ulogic_vector(31 downto 0)) return std_ulogic_vector is function popcnt32(val: std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
variable ret: unsigned(5 downto 0) := (others => '0'); variable ret: unsigned(5 downto 0) := (others => '0');
begin begin
for i in val'range loop for i in val'range loop
ret := ret + ("00000" & val(i)); ret := ret + ("00000" & val(i));
end loop; end loop;


return std_ulogic_vector(resize(ret, val'length)); return std_ulogic_vector(resize(ret, val'length));
end; end;


function popcnt64(val: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is function popcnt64(val: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
variable ret: unsigned(6 downto 0) := (others => '0'); variable ret: unsigned(6 downto 0) := (others => '0');
begin begin
for i in val'range loop for i in val'range loop
ret := ret + ("000000" & val(i)); ret := ret + ("000000" & val(i));
end loop; end loop;


return std_ulogic_vector(resize(ret, val'length)); return std_ulogic_vector(resize(ret, val'length));
end; end;


function cmp_one_byte(a, b: std_ulogic_vector(7 downto 0)) return std_ulogic_vector is function cmp_one_byte(a, b: std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
variable ret: std_ulogic_vector(7 downto 0); variable ret: std_ulogic_vector(7 downto 0);
begin begin
if a = b then if a = b then
ret := x"ff"; ret := x"ff";
else else
ret := x"00"; ret := x"00";
end if; end if;


return ret; return ret;
end; end;


function ppc_signed_compare(a, b: signed(63 downto 0)) return std_ulogic_vector is function ppc_signed_compare(a, b: signed(63 downto 0)) return std_ulogic_vector is
variable ret: std_ulogic_vector(3 downto 0); variable ret: std_ulogic_vector(3 downto 0);
begin begin
if a < b then if a < b then
ret := "1000"; ret := "1000";
elsif a > b then elsif a > b then
ret := "0100"; ret := "0100";
else else
ret := "0010"; ret := "0010";
end if; end if;


return ret; return ret;
end; end;


function ppc_unsigned_compare(a, b: unsigned(63 downto 0)) return std_ulogic_vector is function ppc_unsigned_compare(a, b: unsigned(63 downto 0)) return std_ulogic_vector is
variable ret: std_ulogic_vector(3 downto 0); variable ret: std_ulogic_vector(3 downto 0);
begin begin
if a < b then if a < b then
ret := "1000"; ret := "1000";
elsif a > b then elsif a > b then
ret := "0100"; ret := "0100";
else else
ret := "0010"; ret := "0010";
end if; end if;


return ret; return ret;
end; end;


function ra_or_zero(ra: std_ulogic_vector(63 downto 0); reg: std_ulogic_vector(4 downto 0)) return std_ulogic_vector is function ra_or_zero(ra: std_ulogic_vector(63 downto 0); reg: std_ulogic_vector(4 downto 0)) return std_ulogic_vector is
begin begin
if to_integer(unsigned(reg)) = 0 then if to_integer(unsigned(reg)) = 0 then
return x"0000000000000000"; return x"0000000000000000";
else else
return ra; return ra;
end if; end if;
end; end;


function byte_reverse(val: std_ulogic_vector(63 downto 0); size: integer) return std_ulogic_vector is function byte_reverse(val: std_ulogic_vector(63 downto 0); size: integer) return std_ulogic_vector is
variable ret : std_ulogic_vector(63 downto 0) := (others => '0'); variable ret : std_ulogic_vector(63 downto 0) := (others => '0');
begin begin
-- Vivado doesn't support non constant vector slices, so we have to code -- Vivado doesn't support non constant vector slices, so we have to code
-- each of these. -- each of these.
case_0: case size is case_0: case size is
when 2 => when 2 =>
for_2 : for k in 0 to 1 loop for_2 : for k in 0 to 1 loop
ret(((8*k)+7) downto (8*k)) := val((8*(1-k)+7) downto (8*(1-k))); ret(((8*k)+7) downto (8*k)) := val((8*(1-k)+7) downto (8*(1-k)));
end loop; end loop;
when 4 => when 4 =>
for_4 : for k in 0 to 3 loop for_4 : for k in 0 to 3 loop
ret(((8*k)+7) downto (8*k)) := val((8*(3-k)+7) downto (8*(3-k))); ret(((8*k)+7) downto (8*k)) := val((8*(3-k)+7) downto (8*(3-k)));
end loop; end loop;
when 8 => when 8 =>
for_8 : for k in 0 to 7 loop for_8 : for k in 0 to 7 loop
ret(((8*k)+7) downto (8*k)) := val((8*(7-k)+7) downto (8*(7-k))); ret(((8*k)+7) downto (8*k)) := val((8*(7-k)+7) downto (8*(7-k)));
end loop; end loop;
when others => when others =>
report "bad byte reverse length " & integer'image(size) severity failure; report "bad byte reverse length " & integer'image(size) severity failure;
end case; end case;


return ret; return ret;
end; end;


function sign_extend(val: std_ulogic_vector(63 downto 0); size: natural) return std_ulogic_vector is function sign_extend(val: std_ulogic_vector(63 downto 0); size: natural) return std_ulogic_vector is
variable ret : signed(63 downto 0) := (others => '0'); variable ret : signed(63 downto 0) := (others => '0');
variable upper : integer := 0; variable upper : integer := 0;
begin begin
case_0: case size is case_0: case size is
when 2 => when 2 =>
ret := resize(signed(val(15 downto 0)), 64); ret := resize(signed(val(15 downto 0)), 64);
when 4 => when 4 =>
ret := resize(signed(val(31 downto 0)), 64); ret := resize(signed(val(31 downto 0)), 64);
when 8 => when 8 =>
ret := resize(signed(val(63 downto 0)), 64); ret := resize(signed(val(63 downto 0)), 64);
when others => when others =>
report "bad byte reverse length " & integer'image(size) severity failure; report "bad byte reverse length " & integer'image(size) severity failure;
end case; end case;


return std_ulogic_vector(ret); return std_ulogic_vector(ret);


end; end;
end package body helpers; end package body helpers;

Write Preview
Loading…
Cancel
Save