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@ -13,6 +13,7 @@ entity litedram_wrapper is
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DRAM_ABITS : positive;
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DRAM_ALINES : natural;
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DRAM_DLINES : natural;
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DRAM_CKLINES : natural;
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DRAM_PORT_WIDTH : positive;
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-- Pseudo-ROM payload
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@ -69,8 +70,8 @@ entity litedram_wrapper is
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ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_clk_p : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
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ddram_clk_n : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic
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@ -93,8 +94,8 @@ architecture behaviour of litedram_wrapper is
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ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_clk_p : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
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ddram_clk_n : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic;
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