Merge pull request #208 from paulusmack/faster
Make the core go faster Several major improvements in here: - Simple branch predictor - Reduced latency for mispredicted branches and interrupts by removing fetch2 stage - Cache improvements o Request critical dword first on refill o Handle hits while refilling, including on line being refilled o Sizes doubled for both D and I - Loadstore improvements: can now do one load or store every two cycles in most cases - Optimized 2-cycle multiplier for Xilinx 7-series parts using DSP slices - Timing improvements, including: o Stash buffer in decode1 o Reduced width of execute1 result mux o Improved SPR decode in decode1 o Some non-critical operation take a cycle longer so we can break some long combinatorial chains - Core logging: logs 256 bits of info every cycle into a ring buffer, to help with debugging and performance analysis This increases the LUT usage for the "synth" + A35 target from 9182 to 10297 = 12%.pull/211/head
GitHub
commit
b90a0a2139
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Load Diff
@ -1,123 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity fetch2 is
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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stall_in : in std_ulogic;
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flush_in : in std_ulogic;
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-- Results from icache
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i_in : in IcacheToFetch2Type;
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-- Output to decode
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f_out : out Fetch2ToDecode1Type
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);
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end entity fetch2;
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architecture behaviour of fetch2 is
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-- The icache cannot stall, so we need to stash a cycle
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-- of output from it when we stall.
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type reg_internal_type is record
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stash : IcacheToFetch2Type;
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stash_valid : std_ulogic;
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stopped : std_ulogic;
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end record;
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signal r_int, rin_int : reg_internal_type;
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signal r, rin : Fetch2ToDecode1Type;
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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if (r /= rin) then
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report "fetch2 rst:" & std_ulogic'image(rst) &
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" S:" & std_ulogic'image(stall_in) &
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" F:" & std_ulogic'image(flush_in) &
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" T:" & std_ulogic'image(rin.stop_mark) &
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" V:" & std_ulogic'image(rin.valid) &
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" FF:" & std_ulogic'image(rin.fetch_failed) &
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" nia:" & to_hstring(rin.nia);
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end if;
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-- Output state remains unchanged on stall, unless we are flushing
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if rst = '1' or flush_in = '1' or stall_in = '0' then
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r <= rin;
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end if;
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-- Internal state is updated on every clock
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r_int <= rin_int;
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end if;
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end process;
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comb : process(all)
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variable v : Fetch2ToDecode1Type;
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variable v_int : reg_internal_type;
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variable v_i_in : IcacheToFetch2Type;
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begin
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v := r;
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v_int := r_int;
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-- If stalling, stash away the current input from the icache
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if stall_in = '1' and v_int.stash_valid = '0' then
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v_int.stash := i_in;
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v_int.stash_valid := '1';
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end if;
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-- If unstalling, source input from the stash and invalidate it,
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-- otherwise source normally from the icache.
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--
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v_i_in := i_in;
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if v_int.stash_valid = '1' and stall_in = '0' then
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v_i_in := v_int.stash;
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v_int.stash_valid := '0';
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end if;
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v.valid := v_i_in.valid;
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v.stop_mark := v_i_in.stop_mark;
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v.fetch_failed := v_i_in.fetch_failed;
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v.nia := v_i_in.nia;
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v.insn := v_i_in.insn;
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-- Clear stash internal valid bit on flush. We still mark
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-- the stash itself as valid since we still want to override
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-- whatever comes form icache when unstalling, but we'll
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-- override it with something invalid.
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--
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if flush_in = '1' then
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v_int.stash.valid := '0';
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v_int.stash.fetch_failed := '0';
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end if;
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-- If we are flushing or the instruction comes with a stop mark
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-- we tag it as invalid so it doesn't get decoded and executed
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if flush_in = '1' or v.stop_mark = '1' then
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v.valid := '0';
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v.fetch_failed := '0';
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end if;
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-- Clear stash on reset
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if rst = '1' then
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v_int.stash_valid := '0';
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v.valid := '0';
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end if;
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-- Update registers
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rin <= v;
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rin_int <= v_int;
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-- Update outputs
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f_out <= r;
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end process;
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end architecture behaviour;
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@ -0,0 +1,12 @@
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CFLAGS = -O2 -g -Wall -std=c99
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all: fmt_log
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fmt_log: fmt_log.c
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$(CC) -o $@ $^ $(CFLAGS)
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clean:
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rm -f fmt_log
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distclean:
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rm -f *~
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@ -0,0 +1,235 @@
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#include <stddef.h>
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#include <stdlib.h>
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#include <stdio.h>
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typedef unsigned long long u64;
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struct log_entry {
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u64 nia_lo: 42;
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u64 nia_hi: 1;
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u64 ic_ra_valid: 1;
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u64 ic_access_ok: 1;
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u64 ic_is_miss: 1;
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u64 ic_is_hit: 1;
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u64 ic_way: 3;
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u64 ic_state: 1;
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u64 ic_part_nia: 4;
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u64 ic_fetch_failed: 1;
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u64 ic_stall_out: 1;
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u64 ic_wb_stall: 1;
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u64 ic_wb_cyc: 1;
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u64 ic_wb_stb: 1;
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u64 ic_wb_adr: 3;
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u64 ic_wb_ack: 1;
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u64 ic_insn: 32;
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u64 ic_valid: 1;
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u64 d1_valid: 1;
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u64 d1_unit: 2;
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u64 d1_part_nia: 4;
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u64 d1_insn_type: 6;
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u64 d2_bypass_a: 1;
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u64 d2_bypass_b: 1;
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u64 d2_bypass_c: 1;
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u64 d2_stall_out: 1;
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u64 d2_stopped_out: 1;
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u64 d2_valid: 1;
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u64 d2_part_nia: 4;
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u64 e1_flush_out: 1;
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u64 e1_stall_out: 1;
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u64 e1_redirect: 1;
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u64 e1_valid: 1;
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u64 e1_write_enable: 1;
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u64 e1_unused: 3;
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u64 e1_irq_state: 1;
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u64 e1_irq: 1;
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u64 e1_exception: 1;
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u64 e1_msr_dr: 1;
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u64 e1_msr_ir: 1;
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u64 e1_msr_pr: 1;
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u64 e1_msr_ee: 1;
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u64 pad1: 5;
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u64 ls_state: 3;
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u64 ls_dw_done: 1;
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u64 ls_min_done: 1;
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u64 ls_do_valid: 1;
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u64 ls_mo_valid: 1;
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u64 ls_lo_valid: 1;
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u64 ls_eo_except: 1;
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u64 ls_stall_out: 1;
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u64 pad2: 2;
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u64 dc_state: 3;
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u64 dc_ra_valid: 1;
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u64 dc_tlb_way: 3;
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u64 dc_stall_out: 1;
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u64 dc_op: 3;
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u64 dc_do_valid: 1;
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u64 dc_do_error: 1;
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u64 dc_wb_cyc: 1;
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u64 dc_wb_stb: 1;
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u64 dc_wb_ack: 1;
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u64 dc_wb_stall: 1;
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u64 dc_wb_adr: 3;
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u64 cr_wr_mask: 8;
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u64 cr_wr_data: 4;
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u64 cr_wr_enable: 1;
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u64 reg_wr_reg: 6;
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u64 reg_wr_enable: 1;
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u64 reg_wr_data;
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};
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#define FLAG(i, y) (log.i? y: ' ')
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#define FLGA(i, y, z) (log.i? y: z)
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#define PNIA(f) (full_nia[log.f] & 0xff)
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const char *units[4] = { "--", "al", "ls", "?3" };
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const char *ops[64] =
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{
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"illegal", "nop ", "add ", "and ", "attn ", "b ", "bc ", "bcreg ",
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"bperm ", "cmp ", "cmpb ", "cmpeqb ", "cmprb ", "cntz ", "crop ", "darn ",
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"dcbf ", "dcbst ", "dcbt ", "dcbtst ", "dcbz ", "div ", "dive ", "exts ",
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"extswsl", "icbi ", "icbt ", "isel ", "isync ", "ld ", "st ", "maddhd ",
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"maddhdu", "maddld ", "mcrxr ", "mcrxrx ", "mfcr ", "mfmsr ", "mfspr ", "mod ",
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"mtcrf ", "mtmsr ", "mtspr ", "mull64 ", "mulh64 ", "mulh32 ", "or ", "popcnt ",
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"prty ", "rfid ", "rlc ", "rlcl ", "rlcr ", "sc ", "setb ", "shl ",
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"shr ", "sync ", "tlbie ", "trap ", "xor ", "ffail ", "?62 ", "?63 "
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};
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const char *spr_names[13] =
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{
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"lr ", "ctr", "sr0", "sr1", "hr0", "hr1", "sg0", "sg1",
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"sg2", "sg3", "hg0", "hg1", "xer"
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};
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int main(int ac, char **av)
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{
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struct log_entry log;
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u64 full_nia[16];
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long int lineno = 1;
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FILE *f;
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const char *filename;
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int i;
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long int ncompl = 0;
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if (ac != 1 && ac != 2) {
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fprintf(stderr, "Usage: %s [filename]\n", av[0]);
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exit(1);
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}
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f = stdin;
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if (ac == 2) {
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filename = av[1];
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f = fopen(filename, "rb");
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if (f == NULL) {
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perror(filename);
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exit(1);
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}
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}
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for (i = 0; i < 15; ++i)
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full_nia[i] = i << 2;
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while (fread(&log, sizeof(log), 1, f) == 1) {
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full_nia[log.nia_lo & 0xf] = (log.nia_hi? 0xc000000000000000: 0) |
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(log.nia_lo << 2);
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if (lineno % 20 == 1) {
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printf(" fetch1 NIA icache decode1 decode2 execute1 loadstore dcache CR GSPR\n");
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printf(" ---------------- TAHW S -WB-- pN --insn-- pN un op pN byp FR IIE MSR WC SD MM CE SRTO DE -WB-- c ms reg val\n");
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printf(" LdMy t csnSa IA IA it IA abc le srx EPID em tw rd mx tAwp vr csnSa 0 k\n");
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}
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printf("%4ld %c0000%.11llx %c ", lineno,
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(log.nia_hi? 'c': '0'),
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(unsigned long long)log.nia_lo << 2,
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FLAG(ic_stall_out, '|'));
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printf("%c%c%c%d %c %c%c%d%c%c %.2llx ",
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FLGA(ic_ra_valid, ' ', 'T'),
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FLGA(ic_access_ok, ' ', 'X'),
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FLGA(ic_is_hit, 'H', FLGA(ic_is_miss, 'M', ' ')),
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log.ic_way,
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FLAG(ic_state, 'W'),
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FLAG(ic_wb_cyc, 'c'),
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FLAG(ic_wb_stb, 's'),
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log.ic_wb_adr,
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FLAG(ic_wb_stall, 'S'),
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FLAG(ic_wb_ack, 'a'),
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PNIA(ic_part_nia));
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if (log.ic_valid)
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printf("%.8x", log.ic_insn);
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else if (log.ic_fetch_failed)
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printf("!!!!!!!!");
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else
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printf("--------");
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printf(" %c%c %.2llx ",
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FLAG(ic_valid, '>'),
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FLAG(d2_stall_out, '|'),
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PNIA(d1_part_nia));
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if (log.d1_valid)
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printf("%s %s",
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units[log.d1_unit],
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ops[log.d1_insn_type]);
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else
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printf("-- -------");
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printf(" %c%c ",
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FLAG(d1_valid, '>'),
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FLAG(d2_stall_out, '|'));
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printf("%.2llx %c%c%c %c%c ",
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PNIA(d2_part_nia),
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FLAG(d2_bypass_a, 'a'),
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FLAG(d2_bypass_b, 'b'),
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FLAG(d2_bypass_c, 'c'),
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FLAG(d2_valid, '>'),
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FLAG(e1_stall_out, '|'));
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printf("%c%c %c%c%c %c%c%c%c %c%c ",
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FLAG(e1_flush_out, 'F'),
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FLAG(e1_redirect, 'R'),
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FLAG(e1_irq_state, 'w'),
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FLAG(e1_irq, 'I'),
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FLAG(e1_exception, 'X'),
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FLAG(e1_msr_ee, 'E'),
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FLGA(e1_msr_pr, 'u', 's'),
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FLAG(e1_msr_ir, 'I'),
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FLAG(e1_msr_dr, 'D'),
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FLAG(e1_write_enable, 'W'),
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FLAG(e1_valid, 'C'));
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printf("%c %d%d %c%c %c%c %c ",
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FLAG(ls_stall_out, '|'),
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log.ls_state,
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log.ls_dw_done,
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FLAG(ls_mo_valid, 'M'),
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FLAG(ls_min_done, 'm'),
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FLAG(ls_lo_valid, 'C'),
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FLAG(ls_eo_except, 'X'),
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FLAG(ls_do_valid, '>'));
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printf("%d%c%d%d %c%c %c%c%d%c%c ",
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log.dc_state,
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FLAG(dc_ra_valid, 'R'),
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log.dc_tlb_way,
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log.dc_op,
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FLAG(dc_do_valid, 'V'),
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FLAG(dc_do_error, 'E'),
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FLAG(dc_wb_cyc, 'c'),
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FLAG(dc_wb_stb, 's'),
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log.dc_wb_adr,
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FLAG(dc_wb_stall, 'S'),
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FLAG(dc_wb_ack, 'a'));
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if (log.cr_wr_enable)
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printf("%x>%.2x ", log.cr_wr_data, log.cr_wr_mask);
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else
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printf(" ");
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if (log.reg_wr_enable) {
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if (log.reg_wr_reg < 32 || log.reg_wr_reg > 44)
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printf("r%02d", log.reg_wr_reg);
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else
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printf("%s", spr_names[log.reg_wr_reg - 32]);
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printf("=%.16llx", log.reg_wr_data);
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}
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printf("\n");
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++lineno;
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if (log.ls_lo_valid || log.e1_valid)
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++ncompl;
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}
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printf("%ld instructions completed, %.2f CPI\n", ncompl,
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(double)(lineno - 1) / ncompl);
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exit(0);
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}
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Binary file not shown.
@ -0,0 +1,985 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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library unisim;
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use unisim.vcomponents.all;
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entity multiply is
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port (
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clk : in std_logic;
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m_in : in Execute1ToMultiplyType;
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m_out : out MultiplyToExecute1Type
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);
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end entity multiply;
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architecture behaviour of multiply is
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signal m00_p, m01_p, m02_p, m03_p : std_ulogic_vector(47 downto 0);
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signal m00_pc : std_ulogic_vector(47 downto 0);
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signal m10_p, m11_p, m12_p, m13_p : std_ulogic_vector(47 downto 0);
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signal m11_pc, m12_pc, m13_pc : std_ulogic_vector(47 downto 0);
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signal m20_p, m21_p, m22_p, m23_p : std_ulogic_vector(47 downto 0);
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signal s0_pc, s1_pc : std_ulogic_vector(47 downto 0);
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signal product_lo : std_ulogic_vector(31 downto 0);
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signal product : std_ulogic_vector(127 downto 0);
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signal addend : std_ulogic_vector(127 downto 0);
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signal s0_carry, p0_carry : std_ulogic_vector(3 downto 0);
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signal p0_mask : std_ulogic_vector(47 downto 0);
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signal p0_pat, p0_patb : std_ulogic;
|
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signal p1_pat, p1_patb : std_ulogic;
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|
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signal req_32bit, r32_1 : std_ulogic;
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signal req_neg, rneg_1 : std_ulogic;
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signal valid_1 : std_ulogic;
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|
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begin
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addend <= (others => m_in.neg_result);
|
||||
|
||||
m00: DSP48E1
|
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generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
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||||
A => "0000000" & m_in.data1(22 downto 0),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(16 downto 0),
|
||||
BCIN => (others => '0'),
|
||||
C => "00000000000000" & addend(33 downto 0),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m00_p,
|
||||
PCIN => (others => '0'),
|
||||
PCOUT => m00_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m01: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "0000000" & m_in.data1(22 downto 0),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(33 downto 17),
|
||||
BCIN => (others => '0'),
|
||||
C => (others => '0'),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "1010101",
|
||||
P => m01_p,
|
||||
PCIN => m00_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m02: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "0000000" & m_in.data1(22 downto 0),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(50 downto 34),
|
||||
BCIN => (others => '0'),
|
||||
C => x"0000000" & "000" & addend(50 downto 34),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m02_p,
|
||||
PCIN => (others => '0'),
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m03: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "0000000" & m_in.data1(22 downto 0),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => "00000" & m_in.data2(63 downto 51),
|
||||
BCIN => (others => '0'),
|
||||
C => x"000000" & '0' & addend(73 downto 51),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m03_p,
|
||||
PCIN => (others => '0'),
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m10: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
CREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "0000000000000" & m_in.data1(39 downto 23),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(16 downto 0),
|
||||
BCIN => (others => '0'),
|
||||
C => x"000" & "00" & m01_p(39 downto 6),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '0',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m10_p,
|
||||
PCIN => (others => '0'),
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m11: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
CREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "0000000000000" & m_in.data1(39 downto 23),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(33 downto 17),
|
||||
BCIN => (others => '0'),
|
||||
C => x"000" & "00" & m02_p(39 downto 6),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '0',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m11_p,
|
||||
PCIN => (others => '0'),
|
||||
PCOUT => m11_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m12: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
CREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "0000000000000" & m_in.data1(39 downto 23),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(50 downto 34),
|
||||
BCIN => (others => '0'),
|
||||
C => x"0000" & '0' & m03_p(36 downto 6),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '0',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m12_p,
|
||||
PCIN => (others => '0'),
|
||||
PCOUT => m12_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m13: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "0000000000000" & m_in.data1(39 downto 23),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => "00000" & m_in.data2(63 downto 51),
|
||||
BCIN => (others => '0'),
|
||||
C => x"0000000" & "000" & addend(90 downto 74),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m13_p,
|
||||
PCIN => (others => '0'),
|
||||
PCOUT => m13_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m20: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "000000" & m_in.data1(63 downto 40),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(16 downto 0),
|
||||
BCIN => (others => '0'),
|
||||
C => (others => '0'),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0010101",
|
||||
P => m20_p,
|
||||
PCIN => m11_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m21: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "000000" & m_in.data1(63 downto 40),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(33 downto 17),
|
||||
BCIN => (others => '0'),
|
||||
C => (others => '0'),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0010101",
|
||||
P => m21_p,
|
||||
PCIN => m12_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m22: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "000000" & m_in.data1(63 downto 40),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => '0' & m_in.data2(50 downto 34),
|
||||
BCIN => (others => '0'),
|
||||
C => (others => '0'),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0010101",
|
||||
P => m22_p,
|
||||
PCIN => m13_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
m23: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 0,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 0,
|
||||
BCASCREG => 0,
|
||||
BREG => 0,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
INMODEREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0
|
||||
)
|
||||
port map (
|
||||
A => "000000" & m_in.data1(63 downto 40),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => "00000" & m_in.data2(63 downto 51),
|
||||
BCIN => (others => '0'),
|
||||
C => x"00" & "000" & addend(127 downto 91),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '0',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '0',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '1',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0110101",
|
||||
P => m23_p,
|
||||
PCIN => (others => '0'),
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
s0: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 1,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 1,
|
||||
BCASCREG => 1,
|
||||
BREG => 1,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
CREG => 1,
|
||||
INMODEREG => 0,
|
||||
MREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0,
|
||||
USE_MULT => "none"
|
||||
)
|
||||
port map (
|
||||
A => m22_p(5 downto 0) & x"0000" & m10_p(34 downto 27),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => m10_p(26 downto 9),
|
||||
BCIN => (others => '0'),
|
||||
C => m20_p(39 downto 0) & m02_p(5 downto 0) & "00",
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CARRYOUT => s0_carry,
|
||||
CEA1 => '0',
|
||||
CEA2 => '1',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '1',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '0',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0001111",
|
||||
PCIN => (others => '0'),
|
||||
PCOUT => s0_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
s1: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 1,
|
||||
ALUMODEREG => 0,
|
||||
AREG => 1,
|
||||
BCASCREG => 1,
|
||||
BREG => 1,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
CREG => 1,
|
||||
INMODEREG => 0,
|
||||
MREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0,
|
||||
USE_MULT => "none"
|
||||
)
|
||||
port map (
|
||||
A => x"000" & m22_p(41 downto 24),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "0000",
|
||||
B => m22_p(23 downto 6),
|
||||
BCIN => (others => '0'),
|
||||
C => m23_p(36 downto 0) & x"00" & "0" & m20_p(41 downto 40),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => s0_carry(3),
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '1',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '0',
|
||||
CEB1 => '0',
|
||||
CEB2 => '1',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '0',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0001111",
|
||||
PCIN => (others => '0'),
|
||||
PCOUT => s1_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
-- mask is 0 for 32-bit ops, 0x0000ffffffff for 64-bit
|
||||
p0_mask(47 downto 31) <= (others => '0');
|
||||
p0_mask(30 downto 0) <= (others => not r32_1);
|
||||
|
||||
p0: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 1,
|
||||
ALUMODEREG => 1,
|
||||
AREG => 1,
|
||||
BCASCREG => 1,
|
||||
BREG => 1,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
CREG => 1,
|
||||
INMODEREG => 0,
|
||||
MREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0,
|
||||
SEL_MASK => "C",
|
||||
USE_MULT => "none",
|
||||
USE_PATTERN_DETECT => "PATDET"
|
||||
)
|
||||
port map (
|
||||
A => m21_p(22 downto 0) & m03_p(5 downto 0) & '0',
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "00" & rneg_1 & '0',
|
||||
B => (others => '0'),
|
||||
BCIN => (others => '0'),
|
||||
C => p0_mask,
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => '0',
|
||||
CARRYINSEL => "000",
|
||||
CARRYOUT => p0_carry,
|
||||
CEA1 => '0',
|
||||
CEA2 => '1',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '1',
|
||||
CEB1 => '0',
|
||||
CEB2 => '1',
|
||||
CEC => '1',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '0',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0010011",
|
||||
P => product(79 downto 32),
|
||||
PATTERNDETECT => p0_pat,
|
||||
PATTERNBDETECT => p0_patb,
|
||||
PCIN => s0_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
p1: DSP48E1
|
||||
generic map (
|
||||
ACASCREG => 1,
|
||||
ALUMODEREG => 1,
|
||||
AREG => 1,
|
||||
BCASCREG => 1,
|
||||
BREG => 1,
|
||||
CARRYINREG => 0,
|
||||
CARRYINSELREG => 0,
|
||||
CREG => 0,
|
||||
INMODEREG => 0,
|
||||
MASK => x"000000000000",
|
||||
MREG => 0,
|
||||
OPMODEREG => 0,
|
||||
PREG => 0,
|
||||
USE_MULT => "none",
|
||||
USE_PATTERN_DETECT => "PATDET"
|
||||
)
|
||||
port map (
|
||||
A => x"0000000" & '0' & m21_p(41),
|
||||
ACIN => (others => '0'),
|
||||
ALUMODE => "00" & rneg_1 & '0',
|
||||
B => m21_p(40 downto 23),
|
||||
BCIN => (others => '0'),
|
||||
C => (others => '0'),
|
||||
CARRYCASCIN => '0',
|
||||
CARRYIN => p0_carry(3),
|
||||
CARRYINSEL => "000",
|
||||
CEA1 => '0',
|
||||
CEA2 => '1',
|
||||
CEAD => '0',
|
||||
CEALUMODE => '1',
|
||||
CEB1 => '0',
|
||||
CEB2 => '1',
|
||||
CEC => '0',
|
||||
CECARRYIN => '0',
|
||||
CECTRL => '0',
|
||||
CED => '0',
|
||||
CEINMODE => '0',
|
||||
CEM => '0',
|
||||
CEP => '0',
|
||||
CLK => clk,
|
||||
D => (others => '0'),
|
||||
INMODE => "00000",
|
||||
MULTSIGNIN => '0',
|
||||
OPMODE => "0010011",
|
||||
P => product(127 downto 80),
|
||||
PATTERNDETECT => p1_pat,
|
||||
PATTERNBDETECT => p1_patb,
|
||||
PCIN => s1_pc,
|
||||
RSTA => '0',
|
||||
RSTALLCARRYIN => '0',
|
||||
RSTALUMODE => '0',
|
||||
RSTB => '0',
|
||||
RSTC => '0',
|
||||
RSTCTRL => '0',
|
||||
RSTD => '0',
|
||||
RSTINMODE => '0',
|
||||
RSTM => '0',
|
||||
RSTP => '0'
|
||||
);
|
||||
|
||||
product(31 downto 0) <= product_lo xor (31 downto 0 => req_neg);
|
||||
|
||||
mult_out: process(all)
|
||||
variable ov : std_ulogic;
|
||||
begin
|
||||
-- set overflow if the high bits are neither all zeroes nor all ones
|
||||
if req_32bit = '0' then
|
||||
ov := not ((p1_pat and p0_pat) or (p1_patb and p0_patb));
|
||||
else
|
||||
ov := not ((p1_pat and p0_pat and not product(31)) or
|
||||
(p1_patb and p0_patb and product(31)));
|
||||
end if;
|
||||
|
||||
m_out.result <= product;
|
||||
m_out.overflow <= ov;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
product_lo <= m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0);
|
||||
m_out.valid <= valid_1;
|
||||
valid_1 <= m_in.valid;
|
||||
req_32bit <= r32_1;
|
||||
r32_1 <= m_in.is_32bit;
|
||||
req_neg <= rneg_1;
|
||||
rneg_1 <= m_in.neg_result;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture behaviour;
|
||||
Loading…
Reference in New Issue