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decode1: Split instruction decoding into two steps

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This reduces the block RAM requirements for instruction decoding by
splitting it into two steps.  The first, in a new pipeline stage
called decode0 (implemented by code in decode1.vhdl) maps the
instruction to a 9-bit instruction code using major and row decode
ROMs.  The second maps the 9-bit code to the final decode_rom_t (about
44 bits wide).  Branch prediction done in decode is now done in
decode0 rather than decode1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
pull/382/head
Paul Mackerras 2 years ago
parent 5380d80039
commit c3ee10f013
3 changed files with 1145 additions and 532 deletions
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2
common.vhdl
Unescape Escape View File

@ -250,6 +250,8 @@ package common is
next_predicted: std_ulogic; next_predicted: std_ulogic;
next_pred_ntaken: std_ulogic; next_pred_ntaken: std_ulogic;
end record; end record;
constant IcacheToDecode1Init : IcacheToDecode1Type :=
(nia => (others => '0'), insn => (others => '0'), others => '0');


type IcacheEventType is record type IcacheEventType is record
icache_miss : std_ulogic; icache_miss : std_ulogic;

1384
decode1.vhdl
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File diff suppressed because it is too large Load Diff

285
decode_types.vhdl
Unescape Escape View File

@ -24,6 +24,291 @@ package decode_types is
OP_ADDG6S, OP_ADDG6S,
OP_FETCH_FAILED OP_FETCH_FAILED
); );

type insn_code is (
INSN_illegal,
INSN_fetch_fail,
INSN_add,
INSN_addc,
INSN_adde,
INSN_addex,
INSN_addg6s,
INSN_addi,
INSN_addic,
INSN_addic_dot,
INSN_addis,
INSN_addme,
INSN_addpcis,
INSN_addze,
INSN_and,
INSN_andc,
INSN_andi_dot,
INSN_andis_dot,
INSN_attn,
INSN_b,
INSN_bc,
INSN_bcctr,
INSN_bclr,
INSN_bctar,
INSN_bperm,
INSN_cbcdtd,
INSN_cdtbcd,
INSN_cmp,
INSN_cmpb,
INSN_cmpeqb,
INSN_cmpi,
INSN_cmpl,
INSN_cmpli,
INSN_cmprb,
INSN_cntlzd,
INSN_cntlzw,
INSN_cnttzd,
INSN_cnttzw,
INSN_crand,
INSN_crandc,
INSN_creqv,
INSN_crnand,
INSN_crnor,
INSN_cror,
INSN_crorc,
INSN_crxor,
INSN_darn,
INSN_dcbf,
INSN_dcbst,
INSN_dcbt,
INSN_dcbtst,
INSN_dcbz,
INSN_divd,
INSN_divde,
INSN_divdeu,
INSN_divdu,
INSN_divw,
INSN_divwe,
INSN_divweu,
INSN_divwu,
INSN_eieio,
INSN_eqv,
INSN_extsb,
INSN_extsh,
INSN_extsw,
INSN_extswsli,
INSN_fabs,
INSN_fadd,
INSN_fadds,
INSN_fcfid,
INSN_fcfids,
INSN_fcfidu,
INSN_fcfidus,
INSN_fcmpo,
INSN_fcmpu,
INSN_fcpsgn,
INSN_fctid,
INSN_fctidu,
INSN_fctiduz,
INSN_fctidz,
INSN_fctiw,
INSN_fctiwu,
INSN_fctiwuz,
INSN_fctiwz,
INSN_fdiv,
INSN_fdivs,
INSN_fmadd,
INSN_fmadds,
INSN_fmr,
INSN_fmrgew,
INSN_fmrgow,
INSN_fmsub,
INSN_fmsubs,
INSN_fmul,
INSN_fmuls,
INSN_fnabs,
INSN_fneg,
INSN_fnmadd,
INSN_fnmadds,
INSN_fnmsub,
INSN_fnmsubs,
INSN_fre,
INSN_fres,
INSN_frim,
INSN_frin,
INSN_frip,
INSN_friz,
INSN_frsp,
INSN_frsqrte,
INSN_frsqrtes,
INSN_fsel,
INSN_fsqrt,
INSN_fsqrts,
INSN_fsub,
INSN_fsubs,
INSN_ftdiv,
INSN_ftsqrt,
INSN_icbi,
INSN_icbt,
INSN_isel,
INSN_isync,
INSN_lbarx,
INSN_lbz,
INSN_lbzcix,
INSN_lbzu,
INSN_lbzux,
INSN_lbzx,
INSN_ld,
INSN_ldarx,
INSN_ldbrx,
INSN_ldcix,
INSN_ldu,
INSN_ldux,
INSN_ldx,
INSN_lfd,
INSN_lfdu,
INSN_lfdux,
INSN_lfdx,
INSN_lfiwax,
INSN_lfiwzx,
INSN_lfs,
INSN_lfsu,
INSN_lfsux,
INSN_lfsx,
INSN_lha,
INSN_lharx,
INSN_lhau,
INSN_lhaux,
INSN_lhax,
INSN_lhbrx,
INSN_lhz,
INSN_lhzcix,
INSN_lhzu,
INSN_lhzux,
INSN_lhzx,
INSN_lwa,
INSN_lwarx,
INSN_lwaux,
INSN_lwax,
INSN_lwbrx,
INSN_lwz,
INSN_lwzcix,
INSN_lwzu,
INSN_lwzux,
INSN_lwzx,
INSN_maddhd,
INSN_maddhdu,
INSN_maddld,
INSN_mcrf,
INSN_mcrfs,
INSN_mcrxrx,
INSN_mfcr,
INSN_mffs,
INSN_mfmsr,
INSN_mfspr,
INSN_modsd,
INSN_modsw,
INSN_modud,
INSN_moduw,
INSN_mtcrf,
INSN_mtfsb,
INSN_mtfsf,
INSN_mtfsfi,
INSN_mtmsr,
INSN_mtmsrd,
INSN_mtspr,
INSN_mulhd,
INSN_mulhdu,
INSN_mulhw,
INSN_mulhwu,
INSN_mulld,
INSN_mulli,
INSN_mullw,
INSN_nand,
INSN_neg,
INSN_nop,
INSN_nor,
INSN_or,
INSN_orc,
INSN_ori,
INSN_oris,
INSN_popcntb,
INSN_popcntd,
INSN_popcntw,
INSN_prtyd,
INSN_prtyw,
INSN_rfid,
INSN_rldcl,
INSN_rldcr,
INSN_rldic,
INSN_rldicl,
INSN_rldicr,
INSN_rldimi,
INSN_rlwimi,
INSN_rlwinm,
INSN_rlwnm,
INSN_sc,
INSN_setb,
INSN_slbia,
INSN_sld,
INSN_slw,
INSN_srad,
INSN_sradi,
INSN_sraw,
INSN_srawi,
INSN_srd,
INSN_srw,
INSN_stb,
INSN_stbcix,
INSN_stbcx,
INSN_stbu,
INSN_stbux,
INSN_stbx,
INSN_std,
INSN_stdbrx,
INSN_stdcix,
INSN_stdcx,
INSN_stdu,
INSN_stdux,
INSN_stdx,
INSN_stfd,
INSN_stfdu,
INSN_stfdux,
INSN_stfdx,
INSN_stfiwx,
INSN_stfs,
INSN_stfsu,
INSN_stfsux,
INSN_stfsx,
INSN_sth,
INSN_sthbrx,
INSN_sthcix,
INSN_sthcx,
INSN_sthu,
INSN_sthux,
INSN_sthx,
INSN_stw,
INSN_stwbrx,
INSN_stwcix,
INSN_stwcx,
INSN_stwu,
INSN_stwux,
INSN_stwx,
INSN_subf,
INSN_subfc,
INSN_subfe,
INSN_subfic,
INSN_subfme,
INSN_subfze,
INSN_sync,
INSN_td,
INSN_tdi,
INSN_tlbie,
INSN_tlbiel,
INSN_tlbsync,
INSN_tw,
INSN_twi,
INSN_wait,
INSN_xor,
INSN_xori,
INSN_xoris
);

type input_reg_a_t is (NONE, RA, RA_OR_ZERO, CIA, FRA); type input_reg_a_t is (NONE, RA, RA_OR_ZERO, CIA, FRA);
type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD, type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD,
CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, FRB); CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, FRB);

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