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@ -1121,7 +1121,6 @@ begin
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rams: for i in 0 to NUM_WAYS-1 generate
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rams: for i in 0 to NUM_WAYS-1 generate
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signal do_read : std_ulogic;
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signal do_read : std_ulogic;
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signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
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signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
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signal do_write : std_ulogic;
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signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
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signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
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signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
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signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
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signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
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signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
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