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@ -84,7 +84,8 @@ architecture rtl of dcache is
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-- TAG_WIDTH is the width in bits of each way of the tag RAM
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constant TAG_WIDTH : natural := TAG_BITS + 7 - ((TAG_BITS + 7) mod 8);
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-- WAY_BITS is the number of bits to select a way
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constant WAY_BITS : natural := log2(NUM_WAYS);
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-- Make sure this is at least 1, to avoid 0-element vectors
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constant WAY_BITS : natural := maximum(log2(NUM_WAYS), 1);
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-- Example of layout for 32 lines of 64 bytes:
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--
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@ -130,7 +131,7 @@ architecture rtl of dcache is
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-- L1 TLB.
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constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
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constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
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constant TLB_WAY_BITS : natural := maximum(log2(TLB_NUM_WAYS), 1);
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constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
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constant TLB_TAG_WAY_BITS : natural := TLB_NUM_WAYS * TLB_EA_TAG_BITS;
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constant TLB_PTE_BITS : natural := 64;
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@ -747,13 +748,15 @@ begin
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end if;
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elsif tlbwe = '1' then
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assert not is_X(tlb_req_index);
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repl_way := to_unsigned(0, TLB_WAY_BITS);
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if TLB_NUM_WAYS > 1 then
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if tlb_hit = '1' then
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repl_way := tlb_hit_way;
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else
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assert not is_X(tlb_plru_victim(to_integer(tlb_req_index)));
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repl_way := unsigned(tlb_plru_victim(to_integer(tlb_req_index)));
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end if;
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assert not is_X(repl_way);
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end if;
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eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
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tagset := tlb_tag_way;
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write_tlb_tag(to_integer(repl_way), tagset, eatag);
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@ -974,12 +977,15 @@ begin
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end if;
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-- The way to replace on a miss
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replace_way <= to_unsigned(0, WAY_BITS);
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if NUM_WAYS > 1 then
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if r1.write_tag = '1' then
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assert not is_X(r1.store_index);
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replace_way <= unsigned(plru_victim(to_integer(r1.store_index)));
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else
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replace_way <= r1.store_way;
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end if;
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end if;
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-- See if the request matches the line currently being reloaded
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if r1.state = RELOAD_WAIT_ACK and rel_match = '1' then
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