PMU: Fix PMC5/6 behaviour when MMCR0[PMCC] = 11

The architecture states that when MMCR0[PMCC] = 0b11, PMC5 and PMC6
are not part of the Performance Monitor, meaning that they are not
controlled by bits in MMCRs, and counter negative conditions in PMCs 5
and 6 don't generate Performance Monitor alerts, exceptions or
interrupts.  It doesn't say that PMC5 and PMC6 are frozen in this
case, so presumably they should continue to count run instructions and
run cycles.

This implements that behaviour.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

pmu.vhdl

@@ -227,7 +227,12 @@ begin
             event := '1';
         end if;
         if mmcr0(MMCR0_PMCjCE) = '1' and
-            (pmcs(2)(31) or pmcs(3)(31) or pmcs(4)(31) or pmcs(5)(31) or pmcs(6)(31)) = '1' then
+            (pmcs(2)(31) or pmcs(3)(31) or pmcs(4)(31)) = '1' then
+            event := '1';
+        end if;
+        if mmcr0(MMCR0_PMCjCE) = '1' and
+            mmcr0(MMCR0_PMCC + 1 downto MMCR0_PMCC) /= "11" and
+            (pmcs(5)(31) or pmcs(6)(31)) = '1' then
             event := '1';
         end if;
 
@@ -309,10 +314,8 @@ begin
             when others =>
         end case;
 
-        if mmcr0(MMCR0_PMCC + 1 downto MMCR0_PMCC) /= "11" then
         inc(5) := (mmcr0(MMCR0_CC56RUN) or p_in.run) and p_in.occur.instr_complete;
         inc(6) := mmcr0(MMCR0_CC56RUN) or p_in.run;
-        end if;
 
         -- Evaluate freeze conditions
         freeze := mmcr0(MMCR0_FC) or
@@ -346,6 +349,14 @@ begin
             end if;
         end loop;
 
+        -- When MMCR0[PMCC] = "11", PMC5 and PMC6 are not controlled by the
+        -- MMCRs and don't generate events, but do continue to count run
+        -- instructions and run cycles.
+        if mmcr0(MMCR0_PMCC + 1 downto MMCR0_PMCC) = "11" then
+            inc(5) := p_in.run and p_in.occur.instr_complete;
+            inc(6) := p_in.run;
+        end if;
+
         doinc <= inc;
         doevent <= event;
         doalert <= event and mmcr0(MMCR0_PMAE);