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Reformat writeback.vhdl

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/51/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 50a361a5dc
commit e69e79d8af
1 changed files with 95 additions and 95 deletions
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190
writeback.vhdl
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@ -6,106 +6,106 @@ library work;
use work.common.all; use work.common.all;


entity writeback is entity writeback is
port ( port (
clk : in std_ulogic; clk : in std_ulogic;


e_in : in Execute2ToWritebackType; e_in : in Execute2ToWritebackType;
l_in : in Loadstore2ToWritebackType; l_in : in Loadstore2ToWritebackType;
m_in : in MultiplyToWritebackType; m_in : in MultiplyToWritebackType;


w_out : out WritebackToRegisterFileType; w_out : out WritebackToRegisterFileType;
c_out : out WritebackToCrFileType; c_out : out WritebackToCrFileType;


complete_out : out std_ulogic complete_out : out std_ulogic
); );
end entity writeback; end entity writeback;


architecture behaviour of writeback is architecture behaviour of writeback is
type reg_internal_type is record type reg_internal_type is record
complete : std_ulogic; complete : std_ulogic;
end record; end record;
type reg_type is record type reg_type is record
w : WritebackToRegisterFileType; w : WritebackToRegisterFileType;
c : WritebackToCrFileType; c : WritebackToCrFileType;
end record; end record;
signal r, rin : reg_type; signal r, rin : reg_type;
signal r_int, rin_int : reg_internal_type; signal r_int, rin_int : reg_internal_type;
begin begin
writeback_0: process(clk) writeback_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
r <= rin; r <= rin;
r_int <= rin_int; r_int <= rin_int;
end if; end if;
end process; end process;


writeback_1: process(all) writeback_1: process(all)
variable x: std_ulogic_vector(0 downto 0); variable x : std_ulogic_vector(0 downto 0);
variable y: std_ulogic_vector(0 downto 0); variable y : std_ulogic_vector(0 downto 0);
variable z: std_ulogic_vector(0 downto 0); variable z : std_ulogic_vector(0 downto 0);
variable v : reg_type; variable v : reg_type;
variable v_int : reg_internal_type; variable v_int : reg_internal_type;
begin begin
v := r; v := r;
v_int := r_int; v_int := r_int;


x := "" & e_in.valid; x := "" & e_in.valid;
y := "" & l_in.valid; y := "" & l_in.valid;
z := "" & m_in.valid; z := "" & m_in.valid;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure; assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;


x := "" & e_in.write_enable; x := "" & e_in.write_enable;
y := "" & l_in.write_enable; y := "" & l_in.write_enable;
z := "" & m_in.write_reg_enable; z := "" & m_in.write_reg_enable;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure; assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;


assert not(e_in.write_cr_enable = '1' and m_in.write_cr_enable = '1'); assert not(e_in.write_cr_enable = '1' and m_in.write_cr_enable = '1');


v.w := WritebackToRegisterFileInit; v.w := WritebackToRegisterFileInit;
v.c := WritebackToCrFileInit; v.c := WritebackToCrFileInit;


v_int.complete := '0'; v_int.complete := '0';
if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' then if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' then
v_int.complete := '1'; v_int.complete := '1';
end if; end if;


if e_in.write_enable = '1' then if e_in.write_enable = '1' then
v.w.write_reg := e_in.write_reg; v.w.write_reg := e_in.write_reg;
v.w.write_data := e_in.write_data; v.w.write_data := e_in.write_data;
v.w.write_enable := '1'; v.w.write_enable := '1';
end if; end if;


if e_in.write_cr_enable = '1' then if e_in.write_cr_enable = '1' then
v.c.write_cr_enable := '1'; v.c.write_cr_enable := '1';
v.c.write_cr_mask := e_in.write_cr_mask; v.c.write_cr_mask := e_in.write_cr_mask;
v.c.write_cr_data := e_in.write_cr_data; v.c.write_cr_data := e_in.write_cr_data;
end if; end if;


if l_in.write_enable = '1' then if l_in.write_enable = '1' then
v.w.write_reg := l_in.write_reg; v.w.write_reg := l_in.write_reg;
v.w.write_data := l_in.write_data; v.w.write_data := l_in.write_data;
v.w.write_enable := '1'; v.w.write_enable := '1';
end if; end if;


if m_in.write_reg_enable = '1' then if m_in.write_reg_enable = '1' then
v.w.write_enable := '1'; v.w.write_enable := '1';
v.w.write_reg := m_in.write_reg_nr; v.w.write_reg := m_in.write_reg_nr;
v.w.write_data := m_in.write_reg_data; v.w.write_data := m_in.write_reg_data;
end if; end if;


if m_in.write_cr_enable = '1' then if m_in.write_cr_enable = '1' then
v.c.write_cr_enable := '1'; v.c.write_cr_enable := '1';
v.c.write_cr_mask := m_in.write_cr_mask; v.c.write_cr_mask := m_in.write_cr_mask;
v.c.write_cr_data := m_in.write_cr_data; v.c.write_cr_data := m_in.write_cr_data;
end if; end if;


-- Update registers -- Update registers
rin <= v; rin <= v;
rin_int <= v_int; rin_int <= v_int;


-- Update outputs -- Update outputs
complete_out <= r_int.complete; complete_out <= r_int.complete;
w_out <= r.w; w_out <= r.w;
c_out <= r.c; c_out <= r.c;
end process; end process;
end; end;

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