register_file: Move GPRs into distributed RAM

The register file is currently implemented as a whole pile of individual
1-bit registers instead of LUT memory which is a huge waste of FPGA
space.

This is caused by the output signal exposing the register file to the
outside world for simulation debug.

This removes that output, and moves the dumping of the register file
to the register file module itself. This saves about 8% of fpga on
the little Arty A7-35T.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/80/head
Benjamin Herrenschmidt 5 years ago
parent a2969fa298
commit ec1868f7d2

@ -213,10 +213,6 @@ package common is
write_cr_data : std_ulogic_vector(31 downto 0); write_cr_data : std_ulogic_vector(31 downto 0);
end record; end record;
constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0')); constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));

-- Would prefer not to expose this outside the register file, but ghdl
-- doesn't support external names
type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
end common; end common;


package body common is package body common is

@ -94,9 +94,6 @@ architecture behave of core is
-- Debug status -- Debug status
signal dbg_core_is_stopped: std_ulogic; signal dbg_core_is_stopped: std_ulogic;


-- For sim
signal registers: regfile;

begin begin


core_rst <= dbg_core_rst or rst; core_rst <= dbg_core_rst or rst;
@ -180,12 +177,16 @@ begin
); );


register_file_0: entity work.register_file register_file_0: entity work.register_file
generic map (
SIM => SIM
)
port map ( port map (
clk => clk, clk => clk,
d_in => decode2_to_register_file, d_in => decode2_to_register_file,
d_out => register_file_to_decode2, d_out => register_file_to_decode2,
w_in => writeback_to_register_file, w_in => writeback_to_register_file,
registers_out => registers); sim_dump => terminate
);


cr_file_0: entity work.cr_file cr_file_0: entity work.cr_file
port map ( port map (
@ -277,17 +278,4 @@ begin
terminated_out => terminated_out terminated_out => terminated_out
); );


-- Dump registers if core terminates
sim_terminate_test: if SIM generate
dump_registers: process(all)
begin
if terminate = '1' then
loop_0: for i in 0 to 31 loop
report "REG " & to_hstring(registers(i));
end loop loop_0;
assert false report "end of test" severity failure;
end if;
end process;
end generate;

end behave; end behave;

@ -6,6 +6,9 @@ library work;
use work.common.all; use work.common.all;


entity register_file is entity register_file is
generic (
SIM : boolean := false
);
port( port(
clk : in std_logic; clk : in std_logic;


@ -15,11 +18,12 @@ entity register_file is
w_in : in WritebackToRegisterFileType; w_in : in WritebackToRegisterFileType;


-- debug -- debug
registers_out : out regfile sim_dump : in std_ulogic
); );
end entity register_file; end entity register_file;


architecture behaviour of register_file is architecture behaviour of register_file is
type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
signal registers : regfile := (others => (others => '0')); signal registers : regfile := (others => (others => '0'));
begin begin
-- synchronous writes -- synchronous writes
@ -64,6 +68,17 @@ begin
end if; end if;
end process register_read_0; end process register_read_0;


-- debug -- Dump registers if core terminates
registers_out <= registers; sim_dump_test: if SIM generate
dump_registers: process(all)
begin
if sim_dump = '1' then
loop_0: for i in 0 to 31 loop
report "REG " & to_hstring(registers(i));
end loop loop_0;
assert false report "end of test" severity failure;
end if;
end process;
end generate;

end architecture behaviour; end architecture behaviour;

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