uart: Make 16550 the default

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

fpga/top-arty.vhdl

@@ -24,7 +24,7 @@ entity toplevel is
         LOG_LENGTH         : natural := 512;
         USE_LITEETH        : boolean  := false;
         UART_IS_16550      : boolean  := false;
-        HAS_UART1          : boolean  := false
+        HAS_UART1          : boolean  := true
         );
     port(
         ext_clk   : in  std_ulogic;

fpga/top-generic.vhdl

@@ -12,7 +12,7 @@ entity toplevel is
 	CLK_INPUT     : positive := 100000000;
 	CLK_FREQUENCY : positive := 100000000;
 	DISABLE_FLATTEN_CORE : boolean := false;
-        UART_IS_16550 : boolean  := false
+        UART_IS_16550 : boolean  := true
 	);
     port(
 	ext_clk   : in  std_ulogic;

fpga/top-nexys-video.vhdl

@@ -20,7 +20,7 @@ entity toplevel is
         SPI_FLASH_OFFSET   : integer := 10485760;
         SPI_FLASH_DEF_CKDV : natural := 1;
         SPI_FLASH_DEF_QUAD : boolean := true;
-        UART_IS_16550      : boolean  := false;
+        UART_IS_16550      : boolean := true;
 	);
     port(
 	ext_clk   : in  std_ulogic;

microwatt.core

@@ -315,7 +315,7 @@ parameters:
     datatype    : bool
     description : Use 16550-compatible UART from OpenCores
     paramtype   : generic
-    default     : false
+    default     : true
 
   has_uart1:
     datatype    : bool

soc.vhdl

@@ -63,7 +63,7 @@ entity soc is
         SPI_FLASH_DEF_QUAD : boolean := false;
         LOG_LENGTH         : natural := 512;
         HAS_LITEETH        : boolean := false;
-	UART0_IS_16550     : boolean := false;
+	UART0_IS_16550     : boolean := true;
 	HAS_UART1          : boolean := false
 	);
     port(