FPU: Fix zero result detection in fmadd-family instructions

With the multiply-add instructions, it is possible to get into state
FMADD_6 with R containing a value >= 8.0.  If the value is exactly
8.0, the logic will incorrectly conclude that the result is zero
because it only tests bits up to UNIT_BIT + 2.  Fix this by testing
up to UNIT_BIT + 3, and add a test case to the FPU test that triggers
this situation.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

fpu.vhdl

@@ -2015,7 +2015,7 @@ begin
                 set_r := '0';
                 opsel_r <= RES_SHIFT;
                 re_sel2 <= REXP2_NE;
-                if (r.r(UNIT_BIT + 2) or r_hi_nz or r_lo_nz or (or (r.r(DP_LSB - 1 downto 0)))) = '0' then
+                if (or (r.r(UNIT_BIT + 3 downto 0))) = '0' then
                     -- R is all zeroes but there may be non-zero bits in S
                     -- so shift them into R and set S to 0
                     set_r := '1';

tests/fpu/fpu.c

@@ -1629,6 +1629,8 @@ struct fmavals {
 	  0x41fffffffff00000, 0xc3ffffffffe00000, 0xc1fffffffff00000, 0x43ffffffffe00000 },
 	{ 0x3ff0000000000000, 0x000060fbffffefc1, 0x000060fbffffefc1, FPS_RN_NEAR,
 	  0x0000c1f7ffffdf82, 0x0000000000000000, 0x8000c1f7ffffdf82, 0x8000000000000000 },
+	{ 0x80000000fffffffd, 0x3ff0000000000000, 0x8000000300000003, FPS_UE | FPS_RN_NEAR,
+	  0xdef0000000000000, 0x5ee0000000300000, 0x5ef0000000000000, 0xdee0000000300000 },
 };
 
 int test23(long arg)