cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
1,530 Commits
39 Branches
0 Tags
69 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '185008c907'
${ noResults }
Commit Graph

3 Commits (185008c907eb960a2cf39572873c14dbf0e91a7c)

Author SHA1 Message Date
Paul Mackerras 3e0888ae35 litesdcard: Update generated code 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 1 year ago
Paul Mackerras c1f23e7417 litesdcard: Regenerate verilog code with buffer direction controls 
This regenerates the verilog code from upstream litex plus a patch to
generate outputs from the litesdcard module for controlling
bidirectional buffers between the FPGA and SD card.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 2 years ago
Paul Mackerras 264e609fd4 litesdcard: Name targets by vendor.frequency, not just vendor 
In future we will want to support targets using the same vendor but
running at different clock frequencies.  Since the clock frequency is
a parameter to the gateware generation process, we now name the target
directories as "vendor.frequency", i.e., "xilinx.100e6" and
"lattice.48e6" rather than "xilinx" and "lattice".

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 2 years ago