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microwatt
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caravel-mpw7-20221125
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branch-alias
trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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fpu-typo
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
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boxarty-20211011
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cache-tlb-parameters-2
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caravel-20210105
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nia-debug
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1 Commits (6c4edf80ae2d7696fcafa0b1e07f15a613f4f59f)

Author SHA1 Message Date
Benjamin Herrenschmidt b46f81fae4 Wishbone debug module 
This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago