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caravel-mpw7-20221125
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litedram-update
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856 Commits (c87b883a82746dae88b431b4b4046fc43a9448ac)
 

Author SHA1 Message Date
Olof Kindgren 5e56b14125 Add FuseSoC core description file with Nexys A7 support 6 years ago
Olof Kindgren abca85b034 Add constraint file for Nexys A7 6 years ago
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel 6 years ago
Olof Kindgren b5bccc4c13 Add dummy clock generator 6 years ago
Anton Blanchard 37fe8b954c Add a few more FPGA related files 
Add a temporary gcc patch to remove hardware divide instructions.

Also add a firmware.hex file built with a gcc with the above patch.

Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago