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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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unused-sig
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fpu-typo
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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jtag-port-2
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4 Commits (ff0744b7957d8c309fb30328a5aa29056d1d0b94)

Author SHA1 Message Date
Paul Mackerras 965b1cbcfe liteeth: Regenerate from current upstream litex 
Some signals have changed names: "eth_" has been dropped from the
names of the MII/GMII/RGMII signals.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 10 months ago
Benjamin Herrenschmidt d564672a82 Regenerate litedram and liteeth 
Note: There are a few patches to upstream to fix an upstream breakage
of litedram standalone generator, and fix some issues with liteeth
in the way it's used on Wukong. All these have pending pull requests.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 3 years ago
Anton Blanchard 34e10cc52c liteeth: Regenerate from upstream litex 
Unfortunately the CSR layout has shifted on upstream litex, so this
is built with the following litex patch backed out:

aad56a047a33 ("integration/soc: Use CSR automatic allocation.")

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Benjamin Herrenschmidt 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller 
Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago