Commit Graph

1218 Commits (ff63ffdbfd969c7eaeb54e5369b655dea080256c)
 

Author SHA1 Message Date
Michael Neuling ff63ffdbfd
Merge pull request #382 from paulusmack/master
Decode in block RAM and other improvements
2 years ago
Michael Neuling 0073d23e73
Merge pull request #392 from paulusmack/fix-branch-alias
fetch1: Fix bug where BTC entries don't match on MSR[IR]
2 years ago
Paul Mackerras 20f49f06f8 multiply_tb: Fix multiply_tb.vhdl for the new multiplier interface
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras b0aa5340b8 execute1: Make it clear that divide logic is not included when HAS_FPU=true
This adds a "not HAS_FPU" condition in a few places to make it obvious
that logic to interface to the divide unit is not included when we
have an FPU.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras d1e8e62fee Remove option for "short" 16x16 bit multiplier
Now that we have a 33 bit x 33 bit signed multiplier in execute1,
there is really no need for the 16 bit multiplier.  The coremark
results are just as good without it as with it.  This removes the
option for the sake of simplicity.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Michael Neuling f093e30a64 Merge branch 'fix-branch-alias' into branch-alias
Merging Anton's test case for this.

Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling b9efc9a608
Merge pull request #388 from antonblanchard/trace-test
tests/trace: Test trace vs system call interrupt
2 years ago
Paul Mackerras 769f5c3a53 fetch1: Fix bug where BTC entries don't match on MSR[IR]
This fixes a bug in the BTC where entries created for a given address
when MSR[IR] = 0 are used when MSR[IR] = 1 and vice-versa.  The fix is
to include r.virt_mode (which mirrors MSR[IR]) in the tag portion of
the BTC.

Fixes: 0fb207be60 ("fetch1: Implement a simple branch target cache", 2020-12-19)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras e02d8060ed Change the multiplier interface to support signed multipliers
This adds an 'is_signed' signal to MultiplyInputType to indicate
whether the data1 and data2 fields are to be interpreted as signed or
unsigned numbers.

The 'not_result' field is replaced by a 'subtract' field which
provides a more intuitive interface for requesting that the product be
subtracted from the addend rather than added, i.e. subtract = 1 gives
C - A * B, vs. subtract = 0 giving C + A * B.  (Previously the users
of the multipliers got the same effect by complementing the addend and
setting not_result = 1.)

The is_32bit field is removed because it is no longer used now that we
have a separate 32-bit multiplier.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Anton Blanchard 25f93fc17e Add branch alias test
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras af9fe3467c xilinx_mult: Prepare for doing signed multiplication
This rearranges the way that partial products are generated and summed
so that the partial products that could be negative in a signed
multiplier are now sign-extended.  The inputs are still zero-extended,
however.

The overflow detection logic now only detects 64-bit overflow, since
32-bit multiplications are handled in a separate multiplier.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 595a758400 execute1: Add a pipelined 33-bit signed multiplier
This adds a pipelined 33-bit by 33-bit signed multiplier with one
cycle latency to the execute pipeline, and uses it for the mullw,
mulhw and mulhwu instructions.  Because it has one cycle of latency we
can assume that its result is available in the second execute stage
without needing to add busy logic to the second stage.

This adds both a generic version of the multiplier and a
Xilinx-specific version using four DSP slices of the Artix-7.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 58e799b350 predecode: Add more comments to row_predecode_rom and insn_code values
This adds comments to row_predecode_rom to aid understanding how the
columns in the second half of the table are allocated to different
primary opcodes, and to the insn_code values to assist in locating the
code with a given numeric value.  No code change.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 6db626d245 icache: Log 36 bits of instruction rather than 32
This expands the field in the log buffer that stores the instruction
fetched from the icache to 36 bits, so that we get the insn_code and
illegal instruction indication.  To do this, we reclaim 3 unused bits
from execute1's portion and one other unused bit (previously just set
to 0 in core.vhdl).

This also alters the trigger behaviour to stop after one quarter of
the log buffer has been filled with samples after the trigger, or 256
entries, whichever is less.  This is to ensure that the trigger event
doesn't get overwritten when the log buffer is small.

This updates fmt_log to the new log format.  Valid instructions are
printed as a decimal insn_code value followed by the bottom 26 bits of
the instruction.  Illegal instructions are printed as "ill" followed
by the full 32 bits of the instruction.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 30f6574135 predecode: Work around apparent yosys/nextpnr bug
This rearranges the synchronous process here to avoid setting fields
of pred(i) to zero or INSN_illegal when valid_in is '0'.
Experimentally, on ECP5 this acts like an asynchronous reset rather
than a synchronous reset.

Instead, handle possible indeterminate input for simulation by making
the maj_predecode and row_predecode fields of predec_t be unsigned
rather than insn_code (an enumerated type), and setting them to X when
the input word is indeterminate.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 21ab36a0c0 Pre-decode instructions when writing them to icache
This splits out the decoding done in the decode0 step into a separate
predecoder, used when writing instructions into the icache.  The
icache now holds 36 bits per instruction rather than 32.  For valid
instructions, those 36 bits comprise the bottom 26 bits of the
instruction word, a 9-bit insn_code value (which uniquely identifies
the instruction), and a zero in the MSB.  For illegal instructions,
the MSB is one and the full instruction word is in the bottom 32 bits.
Having the full instruction word available for illegal instructions
means that it can be printed in the log when simulating, or in future
could be placed in the HEIR register.

If we don't have an FPU, then the floating-point instructions are
regarded as illegal.  In that case, the insn_code values would fit
into 8 bits, which could be used in future to reduce the size of
decode_rom from 512 to 256 entries.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 26dc1e879c Eliminate use of primary opcode outside of decode1
This changes code that previously looked at the primary opcode (bits
26 to 31) of the instruction to use other methods, in places other
than in stage0 of decode1.

* Extend rc_t to have a new value, RCOE, indicating that the
  instruction has both Rc and OE bits.

* Decode2 now tells execute1 whether the instruction has a third
  operand, used for distinguishing between multiply and multiply-add
  instructions.

* The invert_a field of the decode ROM is overloaded for load/store
  instructions to indicate cache-inhibited loads and stores.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras c9aea45ffe decode1: Divide insn_code values into ranges to indicate register usage
This lets us compute r_out.reg_*_addr and r_out.read_2_enable values
without needing access to the primary opcode value.  We also have that
non-FP instructions are < 256.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras c3ee10f013 decode1: Split instruction decoding into two steps
This reduces the block RAM requirements for instruction decoding by
splitting it into two steps.  The first, in a new pipeline stage
called decode0 (implemented by code in decode1.vhdl) maps the
instruction to a 9-bit instruction code using major and row decode
ROMs.  The second maps the 9-bit code to the final decode_rom_t (about
44 bits wide).  Branch prediction done in decode is now done in
decode0 rather than decode1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 5380d80039 decode1: Use block RAMs in decode
This combines the various decode arrays in decode1 into two, one
indexed by the major opcode (bits 31--26 of the instruction) together
with bits 4--0 of the instruction, and the other indexed mostly by the
minor opcode (bits 10--1), with some swizzles to accommodate the
relevant parts of the minor opcode space for opcodes 19, 31, 59 and 63
within a 2k entry ROM (11 address bits).  These are called the "major"
and the "row" decode ROMs respectively.  (Bits 10--6 of the
instruction are called the "row index", and bits 5--1, or 5--0 for
some opcodes, are called the "column index", because of the way the
opcode maps in the ISA are laid out.)

Both ROMs are looked up each cycle and the result from one or other,
or from an override in ri.override_decode, are selected after a clock
edge.

This uses quite a lot of BRAM resources.  In future a predecode step
will reduce the BRAM usage substantially.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 47895f8aff decode2: Decode unit and single-pipe attributes for mfspr/mtspr in decode2
Instead of doing that in decode1.  That lets us get rid of the
force_single and override_unit fields of reg_internal_t in decode1,
which will simplify following changes to decode1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 09965b9102 FPU: Set sign of 0 result of subtraction in pack_dp
When a floating-point subtraction results in a zero result, the sign
of the result is required to be positive in all rounding modes except
the round to minus infinity mode, when it is negative.  Consolidate
the logic for doing this in one place, in the pack_dp function,
instead of having it at each place where a zero result is generated.

Since fnmadd[s] and fnmsub[s] negate the result after this rule has
been applied, we use the r.negate signal to indicate a negation which
is now done in pack_dp.  Thus the EXC_RESULT state no longer uses
r.negate, and in fact doesn't set v.result_sign at all; that is now
done in the states that lead into EXC_RESULT.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 932da4c114 FPU: Simplify IDLE state code
Do more decoding of the instruction ahead of the IDLE state
processing so that the IDLE state code becomes much simpler.
To make the decoding easier, we now use four insn_type_t codes for
floating-point operations rather than two.  This also rearranges the
insn_type_t values a little to get the 4 FP opcode values to differ
only in the bottom 2 bits, and put OP_DIV, OP_DIVE and OP_MOD next to
them.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 8da05e5331 FPU: Make an explicit exponent data path
With this, the large case statement sets values for a set of control
signals, which then control multiplexers and adders that generate
values for v.result_exp and v.shift.  The plan is for the case
statement to turn into a microcode ROM eventually.

The value of v.result_exp is the sum of two values, either of which
can be negated (but not both).  The first value can be chosen from the
result exponent, A exponent, B exponent arithmetically shifted right
one bit, or 0.  The second value can be chosen from new_exp (which is
r.result_exp - r.shift), B exponent, C exponent or a constant.  The
choices for the constant are 0, 56, the maximum exponent (max_exp) or
the exponent bias for trap-enabled overflow conditions (bias_exp).
These choices are controlled by the signals re_sel1, re_neg1, re_sel2
and re_neg2, and the sum is written into v.result_exp if re_set_result
is 1.

For v.shift we also compute the sum of two values, either of which
can be negated (but not both).  The first value can be chosen from
new_exp, B exponent, r.shift, or 0.  The second value can be chosen
from the A exponent or a constant.  The possible constants are 0, 1,
4, 8, 32, 52, 56, 63, 64, or the minimum exponent (min_exp).  These
choices are controlled by the signals rs_sel1, rs_neg1, rs_sel2 and
rs_neg2.  After the adder there is a multiplexer which selects either
the sum or a shift count for normalization (derived from a count
leading zeroes operation on R) to be written into v.shift.  The
count-leading-zeroes result does not go through the adder for timing
reasons.

In order to simplify the logic and help improve timing, settings of
the control signals have been made unconditional in a state in many
places, even if those settings are only required when some condition
is met.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 03ca9b5dd5 FPU: Minor fix and simplifications
In preparation for an explicit exponent data path.  The fix is that
fre[s] needs to negate the exponent after renomalization rather than
before, otherwise the exponent adjustment done by the renormalization
is in the wrong direction.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 7a60c118ed loadstore1: Simplify address generation in OP_FETCH_FAILED case
Instead of having a multiplexer in loadstore1 in order to be able to
put the instruction address into v.addr, we now set decode.input_reg_a
to CIA in the decode table entry for OP_FETCH_FAILED.  That means that
the operand selection machinery in decode2 will supply the instruction
address to loadstore1 on the lv.addr1 input and no special case is
needed in loadstore1.  This saves a few LUTs (~40 on the Artix-7).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras 795b6e2a6b Remove leftover logic for 16-byte loads and stores
This removes some logic that was previously added for the 16-byte
loads and stores (lq, lqarx, stq, stqcx.) and not completely removed
in commit c9e838b656 ("Remove support for lq, stq, lqarx and
stqcx.", 2022-06-04).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Paul Mackerras fc58559ee8 writeback: Eliminate unintentional inferred latch
By not assigning to interrupt_out.srr1 in some circumstances, the
writeback_1 process creates an inferred latch, which is not
desirable.  Eliminate it by restructuring the code so
interrupt_out.srr1 is always set, to zeroes if nothing else.

Fixes: bc4d02cb0d ("Start removing SPRs from register file", 2022-07-12)
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Michael Neuling 2562053af3
Merge pull request #390 from shenki/fix-whide-warnings
Fix -Whide warnings
2 years ago
Anton Blanchard 3c9b3c39ae
Merge pull request #389 from paulusmack/fix-sc
execute1: Fix trace interrupt on sc instruction
2 years ago
Anton Blanchard 3c27abcc40 tests/trace: Test trace vs system call interrupt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras 939c7e39dd execute1: Fix trace interrupt on sc instruction
This fixes a bug which causes a trace interrupt to store the wrong
value in SRR0 in the case where the instruction that has just
completed is followed by a sc (system call) instruction.  What happens
is that first the traced instruction sets ex1.trace_next.  Then, when
the sc instruction following it comes in, the execute1_actions process
sets v.e.last_nia to next_nia because it is an sc instruction, even
though it is not going to be executed -- we are going to take the
trace interrupt instead.  Then when the trace interrupt is taken, we
incorrectly set SRR0 to the incremented address (the address of the
instruction following the sc).

To fix this, we have execute1_actions set a new flag if the current
instruction is sc, and only set v.e.last_nia to next_nia if we
actually execute the sc (in the "if go = '1'" case).

Fixes: 813e2317bf ("execute1: Restructure to separate out execution of side effects", 2022-06-18)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
Joel Stanley dc6a4b1406 soc: Fix -Whide warning
soc.vhdl:847:9⚠️ declaration of "uart1" hides if generate statement [-Whide]
        uart1: uart_top
        ^

Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years ago
Joel Stanley c6ca844c88 xics: Fix -Whide warnings
xics.vhdl:83:25⚠️ declaration of "v" hides variable "v" [-Whide]
        function  bswap(v : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is

xics.vhdl:84:22⚠️ declaration of "r" hides signal "r" [-Whide]
            variable r : std_ulogic_vector(31 downto 0);

Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years ago
Joel Stanley 60c54fb959 fpu: Fix -Whide warnings
fpu.vhdl:513:18⚠️ declaration of "result" hides signal "result" [-Whide]
         variable result : std_ulogic_vector(63 downto 0);

Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years ago
Michael Neuling 2641e6d5cd
Merge pull request #387 from antonblanchard/gitignore
Add litesdcard/build to gitignore
2 years ago
Anton Blanchard ad37b2e07c Add litesdcard/build to gitignore
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras a2c9c9b3cf
Merge pull request #384 from antonblanchard/litedram-update
Litedram update
2 years ago
Anton Blanchard aa1d2b16d7 litedram: Regenerate
Regenerate from upstream litex. Something in the update has improved
memory read and write performance quite a lot on my Nexys Video:

Before:

  Write speed: 83.2MiB/s
   Read speed: 140.4MiB/s

After:

  Write speed: 352.1MiB/s
   Read speed: 218.5MiB/s

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard e0bf743d7a litedram: MIGEN_GIT_SHA1 no longer defined
MIGEN_GIT_SHA1 is no longer defined in upstream litex, so remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras 2ca21ebcae
Merge pull request #383 from antonblanchard/fix-sdcard
litesdcard: Fix and regenerate Verilog
2 years ago
Anton Blanchard 83fe8b629c litesdcard: Fix and regenerate Verilog
Fix the litex generate script to pass frequencies in Hz. Regenerate
the litesdcard Verilog for both Xilinx and Lattice. This fixes
litesdcard on my Nexys Video.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Paul Mackerras 76a7b98840
Merge pull request #381 from shingarov/gitignore-artifacts
Gitignore build artifacts
2 years ago
Paul Mackerras de8fd492c8
Merge pull request #378 from mikey/ux-cleanup
Metavalue cleanup
2 years ago
Boris Shingarov 8e234ddb5a Gitignore build artifacts
Building the mw_debug program leaves build artifacts in
microwatt/scripts/mw_debug
causing noise in the output of `git status`.
This commit adds them to .gitignore.

Signed-off-by: Boris Shingarov <shingarov@labware.com>
2 years ago
Michael Neuling eeac86c9d8 test: Add test for metavalues
Make sure they don't increase in future

Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 72fcca8e52 tests: Update FPU test output
The following commit added two tests but didn't update the tests
outputs:

    commit 73cc5167ec
    Author: Paul Mackerras <paulus@ozlabs.org>
    Date:   Mon May 9 19:18:42 2022 +1000
    Use FPU for division instructions if we have an FPU

This patch updates these using tests/update_console_tests

Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling f34b2488e4 tests: Minor script cleanups
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 438a76dafd Metavalue cleanup for register_file.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago
Michael Neuling 7a3e5cac3b Metavalue cleanup for pmu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
2 years ago