A tiny Open POWER ISA softcore written in VHDL 2008
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Dan Horák 1ddbacb67f syscon: Implement a register for storing git hash info 3 months ago
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fmt_log icache: Log 36 bits of instruction rather than 32 4 months ago
mw_debug Provide debug access to SPRs in loadstore1 and mmu 4 months ago
bin2hex.py bin2hex: Make sure to generate little endian files 3 years ago
dependencies.py uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 2 years ago
gen_icache_tb.py icache_tb: Improve test and include test file 3 years ago
make_version.sh syscon: Implement a register for storing git hash info 3 months ago
make_version_fusesoc.py syscon: Implement a register for storing git hash info 3 months ago
run_test.sh tests: Minor script cleanups 4 months ago
run_test_console.sh test: Add test for metavalues 4 months ago
test_micropython.py Update micropython 3 years ago
test_micropython_long.py Update micropython 3 years ago
test_micropython_verilator.py makefile: Add some verilator micropython tests 1 year ago
test_micropython_verilator_long.py makefile: Add some verilator micropython tests 1 year ago
vhdltags Add VHDL TAGS 3 years ago