A tiny Open POWER ISA softcore written in VHDL 2008

openpowerppc64leprocessorvhdl

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Branch: master

alt-reset-address

asic-3

boxarty-20211011

branch-alias

cache-tlb-parameters-2

caravel-20210105

caravel-20210114

caravel-mpw5-20220322

caravel-mpw5-20220323

caravel-mpw6-20220530

caravel-mpw7-20220822

caravel-mpw7-20221125

core_debug-init

dcache-nc-fix

dcache-unused-sig

divider-init

fix-sdcard

fpu-constant

fpu-init

fpu-typo

gitignore

icache-insn-u-state

icache-pmu-events

icache-unused-sig

icbi-issue

jtag-port

jtag-port-2

less-fpga-init

litedram-update

liteeth-update

loadstore-init

loadstore-pmu-init

log2ceil-issue

master

nia-debug

orange-crab-freq

remove-potato-uart

trace-test

unused-sig

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microwatt/uart16550

History

Benjamin Herrenschmidt d299ea925e Bundle the uart16550 core file ... We already carry the UART verilog source, so we may as well use it instead of requiring fusesoc to import it from its library Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 months ago
..
raminfr.v	Add uart16550 files from fusesoc	3 years ago
uart16550.core	Bundle the uart16550 core file	5 months ago
uart_defines.v	Add uart16550 files from fusesoc	3 years ago
uart_receiver.v	Add uart16550 files from fusesoc	3 years ago
uart_regs.v	Add uart16550 files from fusesoc	3 years ago
uart_rfifo.v	Add uart16550 files from fusesoc	3 years ago
uart_sync_flops.v	Add uart16550 files from fusesoc	3 years ago
uart_tfifo.v	Add uart16550 files from fusesoc	3 years ago
uart_top.v	Add uart16550 files from fusesoc	3 years ago
uart_transmitter.v	Add uart16550 files from fusesoc	3 years ago
uart_wb.v	Add uart16550 files from fusesoc	3 years ago