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A tiny Open POWER ISA softcore written in VHDL 2008
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Anton Blanchard 1d29cdcfb4 Remove Potato UART 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
.github/workflows ci: Remove noflatten to reduce size of ECP5 builds
constraints Initial support for ghdl synthesis
fpga Remove Potato UART
hello_world Remove Potato UART
include Remove Potato UART
lib Remove Potato UART
litedram litedram: Add sdcard to soc features
liteeth liteeth: Regenerate from upstream litex
litesdcard litesdcard: Use vendor not board type
media Add title image
micropython tests: Add updated micropython build with 16550 support
openocd openocd: Fix verify command for v0.10
rust_lib_demo console: Cleanup console API
scripts decode: Add a facility field to the instruction decode tables
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests tests/fpu: Test FPU unavailable interrupt following a load
uart16550 Add uart16550 files from fusesoc
verilator Pass clock frequency to UART sim wrapper
.gitignore Add yosys builds files to gitignore
LICENSE Initial import of microwatt
Makefile Remove Potato UART
README.md Update documentation. ()
cache_ram.vhdl Reformat cache_ram
common.vhdl execute1: Handle interrupts during sequences of load/store operations
control.vhdl Reformat control
core.vhdl icache: Snoop writes to memory by other agents
core_debug.vhdl Fix some whitespace issues
core_dram_tb.vhdl Reformat testbenches
core_flash_tb.vhdl Reformat testbenches
core_tb.vhdl Reformat testbenches
countzero.vhdl Reformat countzero
countzero_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
cr_file.vhdl Reformat cr_file
crhelpers.vhdl crhelpers: Constraint "crnum" integer
dcache.vhdl dcache: Simplify logic in RELOAD_WAIT_ACK state
dcache_tb.vhdl Reformat testbenches
decode1.vhdl MMU: Implement a vestigial partition table
decode2.vhdl core: Allow multiple loadstore instructions to be in flight
decode_types.vhdl core: Crack update-form loads into two internal ops
divider.vhdl Reformat divider
divider_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl Reformat testbenches
dmi_dtm_xilinx.vhdl Fix some whitespace issues
dram_tb.vhdl Reformat testbenches
execute1.vhdl execute1: Handle interrupts during sequences of load/store operations
fetch1.vhdl core: Move redirect and interrupt delivery logic to writeback
foreign_random.vhdl Make core testbenches recognized by VUnit
fpu.vhdl core: Send FPU interrupts to writeback rather than execute1
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
gpio.vhdl Add a GPIO controller and use it to drive the shield I/O pins on the Arty
helpers.vhdl core: Add support for single-precision FP loads and stores
icache.vhdl icache: Snoop writes to memory by other agents
icache_tb.vhdl Reformat testbenches
icache_test.bin icache_tb: Improve test and include test file
insn_helpers.vhdl core: Implement quadword loads and stores
loadstore1.vhdl execute1: Handle interrupts during sequences of load/store operations
logical.vhdl core: Make result multiplexing explicit
microwatt.core Remove Potato UART
mmu.vhdl MMU: Implement a vestigial partition table
multiply.vhdl execute1: Take an extra cycle for OE=1 multiply instructions
multiply_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
nonrandom.vhdl Add random number generator and implement the darn instruction
plru.vhdl Reformat plru
plru_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
ppc_fx_insns.vhdl Fix some whitespace issues
random.vhdl Make core testbenches recognized by VUnit
register_file.vhdl Reformat register_file
rotator.vhdl Reformat rotator
rotator_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging
run.py VUnit: style
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART
sim_bram.vhdl Fix some whitespace issues
sim_bram_helpers.vhdl ram: Rework main RAM interface
sim_bram_helpers_c.c Consolidate VHPI code
sim_console.vhdl Reformat sim_console
sim_console_c.c sim_console: Fix polling to check for POLLIN
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c Consolidate VHPI code
sim_no_flash.vhdl spi: Add simulation support
sim_vhpi_c.c Consolidate VHPI code
sim_vhpi_c.h Consolidate VHPI code
soc.vhdl Remove Potato UART
spi_flash_ctrl.vhdl Reformat spi_flash_ctrl
spi_rxtx.vhdl Merge pull request from antonblanchard/another-spi-rxtx-reset-issu
sync_fifo.vhdl litedram: Add an L2 cache with store queue
syscon.vhdl Remove Potato UART
utils.vhdl litedram: Add support for booting without BRAM
wishbone_arbiter.vhdl wb_arbiter: Early master selection
wishbone_bram_tb.bin ram: Rework main RAM interface
wishbone_bram_tb.vhdl Reformat testbenches
wishbone_bram_wrapper.vhdl Add log2ceil and use it in bram code
wishbone_debug_master.vhdl Fix some whitespace issues
wishbone_types.vhdl arty_a7: Add litesdcard interface
writeback.vhdl Reformat writeback
xics.vhdl Fix some whitespace issues
xilinx-mult.vhdl execute1: Take an extra cycle for OE=1 multiply instructions

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)