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microwatt/litedram/gen-src
History
Boris Shingarov 0b93f1657e [genesys2] Fix DDR3 PHY cmd_latency 
In the fall of 2020, cmd/clk scan in liblitedram was changed in a way
that required reverting cmd_latency being set to 1 in LiteDRAM commit
4e62d28 back to 0.  For the default in s7ddrphy.py this revert happened
in 496cd27, but for standalone gen the .yml was never updated in neither
LiteDRAM nor Microwatt, leading to regression:
https://github.com/antonblanchard/microwatt/issues/363
The present commit updates the .yml so DRAM works on Genesys2 again.

See also
https://github.com/enjoy-digital/litedram/pull/368
for a corresponding update to the .yml in LiteDRAM.

Signed-off-by: Boris Shingarov <shingarov@labware.com>
 		1 week ago
..
sdram_init ECPIX-5: Wire up SPI flash 1 year ago
acorn-cle-215.yml litedram: disable block_until_ready, regenerate 4 years ago
arty.yml litedram: disable block_until_ready, regenerate 4 years ago
dram-init-mem.vhdl Make wishbone addresses be in units of doublewords or words 4 years ago
ecpix-5.yml ECPIX-5: Add litedram support 1 year ago
generate.py ECPIX-5: Add litedram support 1 year ago
genesys2.yml [genesys2] Fix DDR3 PHY cmd_latency 1 week ago
nexys-video.yml litedram: disable block_until_ready, regenerate 4 years ago
no-init-mem.vhdl litedram: Split the init memory from the main wrapper 5 years ago
orangecrab-85-0.2.yml litedram: Add orangecrab-85-0.2 target 4 years ago
sim.yml litedram: disable block_until_ready, regenerate 4 years ago
wukong-v2.yml litedram: disable block_until_ready, regenerate 4 years ago