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215 lines
8.0 KiB
VHDL
215 lines
8.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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-- Interface for LCD/touchscreen connected to Arduino-compatible socket on Arty A7
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entity lcd_touchscreen is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out;
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wb_sel : in std_ulogic;
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tp : out std_ulogic;
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lcd_din : in std_ulogic_vector(7 downto 0);
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lcd_dout : out std_ulogic_vector(7 downto 0);
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lcd_doe : out std_ulogic;
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lcd_doe0 : out std_ulogic;
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lcd_doe1 : out std_ulogic;
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lcd_rd : out std_ulogic; -- note active low
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lcd_wr : out std_ulogic; -- note active low
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lcd_rs : out std_ulogic;
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lcd_rsoe : out std_ulogic;
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lcd_cs : out std_ulogic; -- note active low
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lcd_csoe : out std_ulogic;
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lcd_rst : out std_ulogic -- note active low
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);
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end entity lcd_touchscreen;
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architecture rtl of lcd_touchscreen is
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type state_t is (idle, prep1, prep2, writing, wr_pause, reading, rd_recovery);
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signal state : state_t;
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signal delay : unsigned(5 downto 0);
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signal ack : std_ulogic;
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signal idle1 : std_ulogic;
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signal idle2 : std_ulogic;
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signal rs : std_ulogic;
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signal rsoe : std_ulogic;
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signal cs : std_ulogic;
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signal csoe : std_ulogic;
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signal d0 : std_ulogic;
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signal doe0 : std_ulogic;
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signal doe1 : std_ulogic;
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signal d1 : std_ulogic;
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signal tsctrl : std_ulogic;
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signal wr_data : std_ulogic_vector(31 downto 0);
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signal rd_data : std_ulogic_vector(7 downto 0);
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signal wr_sel : std_ulogic_vector(3 downto 0);
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signal req_wr : std_ulogic;
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-- Assume touchscreen is connected as follows:
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-- X+ -> A5 (D1), X- -> A3 (CS), Y+ -> A2 (RS), Y- -> A4 (D0)
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begin
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-- for now; should make sure it is at least 10us wide
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lcd_rst <= not rst;
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wb_out.dat <= rd_data & rd_data & rd_data & rd_data;
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wb_out.ack <= ack;
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wb_out.stall <= '0' when state = idle else '1';
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lcd_doe0 <= doe0;
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lcd_doe1 <= doe1;
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lcd_rs <= rs;
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lcd_rsoe <= rsoe;
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lcd_cs <= cs;
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lcd_csoe <= csoe;
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tp <= tsctrl;
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process (clk)
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begin
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if rising_edge(clk) then
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ack <= '0';
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idle2 <= idle1;
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if rst = '1' then
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state <= idle;
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delay <= to_unsigned(0, 6);
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rd_data <= (others => '0');
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lcd_rd <= '1';
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lcd_wr <= '1';
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cs <= '1';
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csoe <= '1';
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rs <= '0';
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rsoe <= '1';
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lcd_doe <= '0';
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doe0 <= '0';
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doe1 <= '0';
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d0 <= '0';
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d1 <= '0';
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idle1 <= '0';
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idle2 <= '0';
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tsctrl <= '0';
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elsif delay /= "000000" then
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delay <= delay - 1;
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else
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case state is
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when idle =>
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req_wr <= wb_in.we;
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wr_data <= wb_in.dat;
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wr_sel <= wb_in.sel;
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if idle2 = '1' then
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-- delay this one cycle after entering idle
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lcd_doe <= '0';
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doe0 <= '0';
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doe1 <= '0';
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end if;
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idle1 <= '0';
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if wb_in.cyc = '1' and wb_in.stb = '1' and wb_sel = '1' then
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if wb_in.sel = "0000" then
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ack <= '1';
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else
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if wb_in.we = '1' or wb_in.adr(2) = '1' then
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ack <= '1';
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end if;
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if wb_in.adr(2) = '0' then
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tsctrl <= '0';
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csoe <= '1';
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cs <= '0'; -- active low
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rsoe <= '1';
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rs <= wb_in.adr(1);
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doe0 <= '0';
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doe1 <= '0';
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state <= prep1;
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else
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tsctrl <= '1';
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idle2 <= '0';
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rd_data <= rsoe & rs & doe0 & d0 & doe1 & d1 & csoe & cs;
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if wb_in.we = '1' and wb_in.sel(0) = '1' then
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rsoe <= wb_in.dat(7);
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rs <= wb_in.dat(6);
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doe0 <= wb_in.dat(5);
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d0 <= wb_in.dat(4);
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lcd_dout(0) <= wb_in.dat(4);
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doe1 <= wb_in.dat(3);
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d1 <= wb_in.dat(2);
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lcd_dout(1) <= wb_in.dat(2);
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csoe <= wb_in.dat(1);
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cs <= wb_in.dat(0);
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end if;
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end if;
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end if;
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else
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if tsctrl = '0' then
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cs <= '1';
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end if;
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end if;
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when prep1 =>
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lcd_doe <= req_wr;
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doe0 <= req_wr;
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doe1 <= req_wr;
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if req_wr = '1' then
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if wr_sel(1 downto 0) /= "00" then
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if wr_sel(1) = '1' then
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lcd_dout <= wr_data(15 downto 8);
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wr_sel(1) <= '0';
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else
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lcd_dout <= wr_data(7 downto 0);
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wr_sel(0) <= '0';
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end if;
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else
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if wr_sel(3) = '1' then
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lcd_dout <= wr_data(31 downto 24);
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wr_sel(3) <= '0';
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else
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lcd_dout <= wr_data(23 downto 16);
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wr_sel(2) <= '0';
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end if;
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end if;
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end if;
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state <= prep2;
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when prep2 =>
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if req_wr = '1' then
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lcd_wr <= '0'; -- active low
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state <= writing;
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delay <= to_unsigned(1, 6);
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else
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lcd_rd <= '0';
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state <= reading;
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delay <= to_unsigned(35, 6);
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end if;
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when writing =>
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-- last cycle of writing state
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lcd_wr <= '1';
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if wr_sel = "0000" then
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state <= idle;
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idle1 <= '1';
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else
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state <= wr_pause;
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end if;
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when wr_pause =>
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state <= prep1;
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when reading =>
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-- last cycle of reading state
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lcd_rd <= '1';
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rd_data <= lcd_din;
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ack <= '1';
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state <= rd_recovery;
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delay <= to_unsigned(6, 6);
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when rd_recovery =>
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state <= idle;
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end case;
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end if;
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end if;
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end process;
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end architecture;
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