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Paul Mackerras
172eae61cb
This adds an interface for an Arduino-compatible LCD touchscreen. The screen module plugs directly on to the Arduino/chipKit shield connector on the Arty A7. Unfortunately, the slightly strange way the resistive touchscreen is brought out (connected to the D0, D1, RS and CS pins) combined with the 200 ohm protection resisters on the Arty board mean that some hardware hacks to the module are necessary. I rewired mine so that D0 and D1 are on the A4 and A5 pins and the reset is where D0 was (shield I/O 8). This interface is suitable for boards with a HX8347 driver chip. The timing may not be quite suitable for other driver chips. The interface is a byte which can be read and written at 0xc8050000, containing an index register, and a 1-8 byte data register at 0xc8050008. Reading at offsets 1 to 7 from those addresses yields the same value as at offset 0. Writing 64 bits to the data register writes the bytes at offset 1, 0, 3, 2, 5, 4, 7, 6 in that order to the driver chip. This allows pixel data to be transferred using 64-bit writes, ending up in the frame buffer in the expected order (for 16-bit pixels, the driver chip expects MS byte then LS byte). 32-bit writes do 1, 0, 3, 2, and 16-bit writes do 1, 0. The touchscreen support so far is a 1-byte register containing bits to set RS, D0, D1 and CS high or low or make them tri-state. There is nothing to do analog conversions of the signal levels at this stage. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
3 days ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| antmicro_artix_dc_scm.xdc | ||
| arty-lcd-ts.vhdl | 3 days ago | |
| arty_a7.xdc | 3 days ago | |
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | ||
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | 8 months ago | |
| top-antmicro-artix-dc-scm.vhdl | ||
| top-arty.vhdl | 3 days ago | |
| top-ecpix5.vhdl | 2 years ago | |
| top-generic.vhdl | ||
| top-genesys2.vhdl | 6 months ago | |
| top-nexys-video.vhdl | 2 years ago | |
| top-orangecrab0.2.vhdl | ||
| top-wukong-v2.vhdl | 2 years ago | |
| wukong-v2.xdc | ||