A tiny Open POWER ISA softcore written in VHDL 2008
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 
Go to file
Benjamin Herrenschmidt 4437487ad0 execute1: Reformat
No functional change

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
fpga Fix clk_gen_bypass 5 years ago
hello_world
media
scripts
sim-unisim
tests
.gitignore
.travis.yml
LICENSE
Makefile Remove execute2 stage 5 years ago
README.md
cache_ram.vhdl
common.vhdl Remove execute2 stage 5 years ago
control.vhdl Add CR hazard detection 5 years ago
core.vhdl Remove execute2 stage 5 years ago
core_debug.vhdl
core_tb.vhdl
countzero.vhdl countzero: Reorganize to have fewer levels of logic and fewer LUTs 5 years ago
countzero_tb.vhdl countzero: Add a testbench 5 years ago
cr_file.vhdl
cr_hazard.vhdl Add CR hazard detection 5 years ago
crhelpers.vhdl
decode1.vhdl Merge pull request #105 from paulusmack/writeback 5 years ago
decode2.vhdl Do sign-extension instructions in writeback instead of execute1 5 years ago
decode_types.vhdl Merge pull request #105 from paulusmack/writeback 5 years ago
divider.vhdl writeback: Do data formatting and condition recording in writeback 5 years ago
divider_tb.vhdl writeback: Do data formatting and condition recording in writeback 5 years ago
dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl
execute1.vhdl execute1: Reformat 5 years ago
fetch1.vhdl
fetch2.vhdl
glibc_random.vhdl
glibc_random_helpers.vhdl
gpr_hazard.vhdl Add GPR hazard detection 5 years ago
helpers.vhdl
icache.vhdl
icache_tb.vhdl
insn_helpers.vhdl
loadstore1.vhdl
loadstore2.vhdl writeback: Do data formatting and condition recording in writeback 5 years ago
logical.vhdl
microwatt.core Remove execute2 stage 5 years ago
multiply.vhdl writeback: Do data formatting and condition recording in writeback 5 years ago
multiply_tb.vhdl writeback: Do data formatting and condition recording in writeback 5 years ago
plru.vhdl
plru_tb.vhdl
ppc_fx_insns.vhdl
register_file.vhdl
rotator.vhdl
rotator_tb.vhdl
sim_console.vhdl
sim_console_c.c
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_uart.vhdl
simple_ram_behavioural.vhdl
simple_ram_behavioural_helpers.vhdl
simple_ram_behavioural_helpers_c.c
simple_ram_behavioural_tb.bin
simple_ram_behavioural_tb.vhdl
soc.vhdl
wishbone_arbiter.vhdl
wishbone_debug_master.vhdl wishbone_debug_master: Improve timing 5 years ago
wishbone_types.vhdl
writeback.vhdl writeback: Remove a mux leg on data_in 5 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)