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71 lines
1.5 KiB
VHDL
71 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity fetch2 is
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port(
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clk : in std_ulogic;
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-- instruction memory interface
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wishbone_in : in wishbone_slave_out;
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wishbone_out : out wishbone_master_out;
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f_in : in Fetch1ToFetch2Type;
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f_out : out Fetch2ToDecode1Type
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);
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end entity fetch2;
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architecture behaviour of fetch2 is
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type reg_type is record
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valid : std_ulogic;
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nia : std_ulogic_vector(63 downto 0);
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end record;
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signal f : Fetch1ToFetch2Type;
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signal wishbone: wishbone_slave_out;
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signal r : reg_type := (valid => '0', nia => (others => '0'));
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signal rin : reg_type := (valid => '0', nia => (others => '0'));
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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wishbone <= wishbone_in;
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f <= f_in;
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r <= rin;
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end if;
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end process;
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comb : process(all)
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variable v : reg_type;
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begin
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v := r;
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if f.valid = '1' then
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v.valid := '1';
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v.nia := f.nia;
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end if;
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if v.valid = '1' and wishbone.ack = '1' then
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v.valid := '0';
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end if;
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rin <= v;
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wishbone_out.adr <= v.nia(63 downto 3) & "000";
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wishbone_out.dat <= (others => '0');
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wishbone_out.cyc <= v.valid;
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wishbone_out.stb <= v.valid;
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wishbone_out.sel <= "00001111" when v.nia(2) = '0' else "11110000";
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wishbone_out.we <= '0';
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f_out.valid <= wishbone.ack;
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f_out.nia <= v.nia;
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f_out.insn <= wishbone.dat(31 downto 0) when v.nia(2) = '0' else wishbone.dat(63 downto 32);
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end process;
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end architecture behaviour;
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