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58 lines
1.3 KiB
VHDL
58 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.wishbone_types.all;
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entity wishbone_arbiter is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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wb1_in : in wishbone_master_out;
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wb1_out : out wishbone_slave_out;
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wb2_in : in wishbone_master_out;
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wb2_out : out wishbone_slave_out;
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wb_out : out wishbone_master_out;
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wb_in : in wishbone_slave_out
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);
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end wishbone_arbiter;
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architecture behave of wishbone_arbiter is
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type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY);
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signal state : wishbone_arbiter_state_t := IDLE;
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begin
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wb1_out <= wb_in when state = WB1_BUSY else wishbone_slave_out_init;
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wb2_out <= wb_in when state = WB2_BUSY else wishbone_slave_out_init;
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wb_out <= wb1_in when state = WB1_BUSY else wb2_in when state = WB2_BUSY else wishbone_master_out_init;
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wishbone_arbiter_process: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= IDLE;
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else
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case state is
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when IDLE =>
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if wb1_in.cyc = '1' then
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state <= WB1_BUSY;
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elsif wb2_in.cyc = '1' then
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state <= WB2_BUSY;
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end if;
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when WB1_BUSY =>
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if wb1_in.cyc = '0' then
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state <= IDLE;
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end if;
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when WB2_BUSY =>
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if wb2_in.cyc = '0' then
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state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process;
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end behave;
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