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98 lines
2.2 KiB
Markdown
98 lines
2.2 KiB
Markdown
# Microwatt
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A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy
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to understand.
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## Simulation using ghdl
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<p align="center">
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<img src="http://neuling.org/microwatt-micropython.gif" alt="MicroPython running on Microwatt"/>
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</p>
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- Build micropython. If you aren't building on a ppc64le box you
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will need a cross compiler. If it isn't available on your distro
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grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
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```
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git clone https://github.com/mikey/micropython
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cd micropython
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git checkout powerpc
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cd ports/powerpc
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make -j$(nproc)
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cd ../../../
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```
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- Microwatt uses ghdl for simulation. Either install this from your
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distro or build it. Next build microwatt:
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```
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git clone https://github.com/antonblanchard/microwatt
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cd microwatt
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make
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```
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- Link in the micropython image:
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```
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ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
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```
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- Now run microwatt, sending debug output to /dev/null:
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```
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./core_tb > /dev/null
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```
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## Synthesis on Xilinx FPGAs using Vivado
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- Install Vivado (I'm using the free 2019.1 webpack edition).
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- Setup Vivado paths:
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```
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source /opt/Xilinx/Vivado/2019.1/settings64.sh
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```
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- Install FuseSoC:
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```
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pip3 install --user -U fusesoc
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```
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- Create a working directory and point FuseSoC at microwatt:
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```
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mkdir microwatt-fusesoc
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cd microwatt-fusesoc
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fusesoc library add microwatt /path/to/microwatt/
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```
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- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
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```
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fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
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```
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- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
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```
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fusesoc run --target=nexys_video microwatt
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```
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## Testing
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- A simple test suite containing random execution test cases and a couple of
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micropython test cases can be run with:
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```
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make -j$(nproc) check
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```
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## Issues
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This is functional, but very simple. We still have quite a lot to do:
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- Need to implement a simple non pipelined divide
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- There are a few instructions still to be implemented
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- Need to add caches and bypassing (in progress)
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- Need to add supervisor state (in progress)
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