A tiny Open POWER ISA softcore written in VHDL 2008
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Anton Blanchard 6cbf456388 SOC memory wishbone should clear ACK regardless of STB
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
fpga SOC memory wishbone should clear ACK regardless of STB 5 years ago
hello_world Rebuild hello world assuming a 50MHz clock 5 years ago
scripts Fix verific script with new VHDL files 5 years ago
tests Initial import of microwatt 5 years ago
.gitignore Add new files to git ignore 5 years ago
.travis.yml Allow a full make check on Travis 5 years ago
LICENSE Initial import of microwatt 5 years ago
Makefile Update Makefile dependencies 5 years ago
README.md Add pretty gif demo of MicroPython on Microwatt to README.md 5 years ago
common.vhdl Remove nia from loadstore and multiply 5 years ago
core.vhdl Reformat core.vhdl 5 years ago
core_tb.vhdl Share soc.vhdl between FPGA and sim 5 years ago
cr_file.vhdl Fix CR forwarding 5 years ago
crhelpers.vhdl Initial import of microwatt 5 years ago
decode1.vhdl Explicitly check against '1' in if statements 5 years ago
decode2.vhdl Merge pull request #47 from antonblanchard/if-fix 5 years ago
decode_types.vhdl Remove sim console 5 years ago
execute1.vhdl Remove FIXME comment 5 years ago
execute2.vhdl Fix issue in execute2 5 years ago
fetch1.vhdl Rework pipeline, add stall and flush signals 5 years ago
fetch2.vhdl Rework pipeline, add stall and flush signals 5 years ago
glibc_random.vhdl Initial import of microwatt 5 years ago
glibc_random_helpers.vhdl Initial import of microwatt 5 years ago
helpers.vhdl Remove dynamic ranges from code 5 years ago
insn_helpers.vhdl Rework decode2 5 years ago
loadstore1.vhdl Fix issue in loadstore1 5 years ago
loadstore2.vhdl Remove second write port 5 years ago
microwatt.core Share soc.vhdl between FPGA and sim 5 years ago
multiply.vhdl Reduce multiply to 2 cycles 5 years ago
multiply_tb.vhdl Initial import of microwatt 5 years ago
ppc_fx_insns.vhdl Remove dynamic ranges from code 5 years ago
register_file.vhdl Add forwarding in the register file 5 years ago
sim_console.vhdl Initial import of microwatt 5 years ago
sim_console_c.c Make sim poll non-blocking 5 years ago
sim_uart.vhdl Share soc.vhdl between FPGA and sim 5 years ago
simple_ram_behavioural.vhdl Share soc.vhdl between FPGA and sim 5 years ago
simple_ram_behavioural_helpers.vhdl Initial import of microwatt 5 years ago
simple_ram_behavioural_helpers_c.c Silence some loadstore related debug 5 years ago
simple_ram_behavioural_tb.bin Initial import of microwatt 5 years ago
simple_ram_behavioural_tb.vhdl Share soc.vhdl between FPGA and sim 5 years ago
soc.vhdl Switch soc to use std_ulogic 5 years ago
wishbone_arbiter.vhdl Initial import of microwatt 5 years ago
wishbone_types.vhdl Remove names from end record statements 5 years ago
writeback.vhdl Register outputs on writeback 5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • Need to implement a simple non pipelined divide
  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)