SOC memory wishbone should clear ACK regardless of STB

The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <>
Anton Blanchard 4 years ago committed by Anton Blanchard
parent 67446709ca
commit 6cbf456388

@ -92,10 +92,8 @@ begin
state <= ACK;
end if;
when ACK =>
if wishbone_in.stb = '0' then
read_ack <= '0';
state <= IDLE;
end if;
read_ack <= '0';
state <= IDLE;
end case;
state <= IDLE;