cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '7f1f6b8525'
${ noResults }
microwatt/litedram/gen-src
History
Benjamin Herrenschmidt 7f1f6b8525 litedram: Add support for Microwatt-initialized controller 
This adds support for initializing the memory controller from microwatt
rather than using a built-in RiscV processor. This might require some
fixes to LiteX and LiteDRAM (they haven't been merged as of this commit
yet).

This is enabled in the shipped generated files and can be changed via
modifying the generator script to pass False to "mw_init"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
sdram_init litedram: Add support for Microwatt-initialized controller 4 years ago
arty.yml litedram: Add support for Microwatt-initialized controller 4 years ago
generate.py litedram: Add support for Microwatt-initialized controller 4 years ago
nexys-video.yml litedram: Add basic support for LiteX LiteDRAM 4 years ago
wrapper-mw-init.vhdl litedram: Add support for Microwatt-initialized controller 4 years ago
wrapper-self-init.vhdl litedram: Add basic support for LiteX LiteDRAM 4 years ago