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master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/scripts
History
Anton Blanchard 9747879643 Add a simple test case 
We use 2 32bit RAMs, so we need to split the test case into
two files.
 		4 years ago
..
fmt_log core: Add framework for an FPU 4 years ago
mw_debug Add core logging 5 years ago
bin2hex-split.py Add a simple test case 4 years ago
bin2hex.py bin2hex: Make sure to generate little endian files 5 years ago
dependencies.py uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 5 years ago
gen_icache_tb.py
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run_test.sh
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run_test_console.sh
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test_micropython.py
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test_micropython_long.py
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vhdltags
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