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Matt Johnston 6be3e1a336 valentyusb: Add USB UART to SOC and OrangeCrab ... An extra uart is added at 0xc0008000 attached to valentyusb, using the OrangeCrab's onboard USB port. This has a liteuart interface, an identifier bit is added to syscon. Generated from branch hw_cdc_eptri of https://github.com/litex-hub/valentyusb The generate script is based on valentyusb/sim/generate_verilog.py UARTUSB: usbserial@8000 { device_type = "serial"; compatible = "litex,liteuart"; reg = <0x8000 0x100>; interrupts = <0x15 0x1>; }; (requires extra kernel patches for early console at present v5.16) Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>		3 years ago
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LICENSE	Initial import of microwatt	5 years ago
acorn-cle-215.xdc	acorn: Add support for the Acorn CLE 215+	4 years ago
arty_a7.xdc	Remove -add from xdc files	3 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_ecp5.vhd	ECP5: Adjust PLL constants so the PLL lock indication works	3 years ago
clk_gen_mcmm.vhd	Fix some whitespace issues	3 years ago
clk_gen_plle2.vhd	fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz	3 years ago
cmod_a7-35.xdc	Remove -add from xdc files	3 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
fpga-random.vhdl	Add random number generator and implement the darn instruction	4 years ago
fpga-random.xdc	Add random number generator and implement the darn instruction	4 years ago
genesys2.xdc	Remove -waveform from xdc files	3 years ago
hello_world.hex	hello_world: Use new headers and frequency from syscon	5 years ago
main_bram.vhdl	Rename 'do' signal to avoid verilator System Verilog warning	3 years ago
nexys-video.xdc	litesdcard: Add Nexys Video support	3 years ago
nexys_a7.xdc	Remove -add from xdc files	3 years ago
pp_fifo.vhd	pp_fifo: Fix full fifo losing all data on simultaneous push & pop	5 years ago
pp_soc_uart.vhd	uart: Remove combinational loops on ack and stall signal	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	soc_reset: Use counters, add synchronizers	5 years ago
soc_reset_tb.vhdl	Exit cleanly from testbench on success	5 years ago
top-acorn-cle-215.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-arty.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-generic.vhdl	core: Add a short multiplier	3 years ago
top-genesys2.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-nexys-video.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
top-orangecrab0.2.vhdl	valentyusb: Add USB UART to SOC and OrangeCrab	3 years ago
top-wukong-v2.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	3 years ago
wukong-v2.xdc	Add support for QMTech Wukong v2 board	3 years ago