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microwatt/fpga
Anton Blanchard a53ad60014 Rename a few reset signals
clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
..
LICENSE
arty_a7-35.xdc Rename a few reset signals 5 years ago
clk_gen_bypass.vhd Add dummy clock generator 5 years ago
clk_gen_plle2.vhd Add and use plle2 primitive for nexys boards 5 years ago
firmware.hex Add a few more FPGA related files 5 years ago
hello_world.hex Rebuild hello world assuming a 50MHz clock 5 years ago
nexys-video.xdc Rename a few reset signals 5 years ago
nexys_a7.xdc Rename a few reset signals 5 years ago
nodivide.patch Add a few more FPGA related files 5 years ago
pp_fifo.vhd
pp_soc_memory.vhd Fix ghdl build error with pp_soc_memory 5 years ago
pp_soc_reset.vhd
pp_soc_uart.vhd
pp_utilities.vhd
toplevel.vhd Rename a few reset signals 5 years ago