A tiny Open POWER ISA softcore written in VHDL 2008
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Michael Neuling b82eea5933
Merge pull request #366 from antonblanchard/hello-world-bss
Zero BSS in hello world test
2 years ago
.github/workflows ci: Add new Orange Crab build 3 years ago
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fpga Extend LiteDRAM VHDL wrapper to allow more than one clock line 3 years ago
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include arty_a7: Add litesdcard interface 4 years ago
lib console: Add support for the 16550 UART 4 years ago
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micropython tests: Add updated micropython build with 16550 support 4 years ago
openocd flash-arty: Add cable argument 3 years ago
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common.vhdl Remove unused sequential signal from Fetch1ToIcacheType 3 years ago
control.vhdl Remove some FPGA style signal inits 3 years ago
core.vhdl Remove some FPGA style signal inits 3 years ago
core_debug.vhdl core_debug: Initialise gspr_index 2 years ago
core_dram_tb.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 3 years ago
core_flash_tb.vhdl Reformat testbenches 4 years ago
core_tb.vhdl Reformat testbenches 4 years ago
countbits.vhdl Use alternative count-leading-zeroes algorithm in the FPU and LSU 3 years ago
countbits_tb.vhdl core: Make popcnt* take two cycles 3 years ago
cr_file.vhdl Reformat cr_file 4 years ago
crhelpers.vhdl crhelpers: Constraint "crnum" integer 5 years ago
dcache.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 3 years ago
dcache_tb.vhdl Reformat testbenches 4 years ago
decode1.vhdl decode1: Conditional trap instructions don't need to be single-issue 3 years ago
decode2.vhdl core: Make popcnt* take two cycles 3 years ago
decode_types.vhdl core: Crack update-form loads into two internal ops 4 years ago
divider.vhdl Reformat divider 4 years ago
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dmi_dtm_dummy.vhdl
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glibc_random_helpers.vhdl
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insn_helpers.vhdl core: Implement quadword loads and stores 4 years ago
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logical.vhdl core: Make popcnt* take two cycles 3 years ago
microwatt.core core: Make popcnt* take two cycles 3 years ago
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multiply.vhdl core: Add a short multiplier 3 years ago
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nonrandom.vhdl Add random number generator and implement the darn instruction 4 years ago
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pmu.vhdl PMU: Add several more events 3 years ago
ppc_fx_insns.vhdl Fix some whitespace issues 3 years ago
random.vhdl Make core testbenches recognized by VUnit 4 years ago
register_file.vhdl Reformat register_file 4 years ago
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sim_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
sim_bram_helpers.vhdl ram: Rework main RAM interface 5 years ago
sim_bram_helpers_c.c Consolidate VHPI code 5 years ago
sim_console.vhdl
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sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c Consolidate VHPI code 5 years ago
sim_no_flash.vhdl spi: Add simulation support 5 years ago
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soc.vhdl Remove some FPGA style signal inits 3 years ago
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spi_rxtx.vhdl Remove some FPGA style signal inits 3 years ago
sync_fifo.vhdl litedram: Add an L2 cache with store queue 5 years ago
syscon.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
utils.vhdl litedram: Add support for booting without BRAM 5 years ago
wishbone_arbiter.vhdl wb_arbiter: Early master selection 5 years ago
wishbone_bram_tb.bin ram: Rework main RAM interface 5 years ago
wishbone_bram_tb.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_bram_wrapper.vhdl wishbone_bram_wrapper ram_addr_bits is 1 bit off 3 years ago
wishbone_debug_master.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_types.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 3 years ago
writeback.vhdl PMU: Add several more events 3 years ago
xics.vhdl xics: Fix warning when comparing two std_ulogic_vectors 3 years ago
xilinx-mult.vhdl core: Add a short multiplier 3 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

  • There are a few instructions still to be implemented:
    • Vector/VMX/VSX