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power-fv/power_fv/insn/spec/compare.py

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In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
from amaranth import *
from power_fv import pfv
from power_fv.insn.const import *
from . import InsnSpec
from .utils import iea
__all__ = ["CompareSpec"]
class CompareSpec(InsnSpec, Elaboratable):
def elaborate(self, platform):
m = Module()
m.d.comb += [
insn: use records to define instruction encodings. Before this commit, instructions were defined by a sequence of Const for fixed fields (e.g. PO/XO) and AnyConst for others (e.g. operands). This approach restricted their use to BMC use-cases, and prevented them from appearing in VCD traces. After this commit, an instruction encoding is defined by a Record. As fields can now be set to arbitrary values, the corresponding InsnSpec will only assert `pfv.stb` if `pfv.insn` matches a valid encoding (i.e. fixed fields have correct values). On the other side, BMC testbenches will drive `pfv.insn` with an AnyConst, and assume `pfv.stb` is high.
2 years ago
self.insn .eq(self.pfv.insn[32:]),
self.pfv.stb .eq(self.insn.is_valid() & ~self.pfv.insn[:32].any()),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
self.pfv.intr.eq(0),
self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
self.pfv.msr.r_mask.sf.eq(1),
self.pfv.xer.r_mask.so.eq(1),
]
insn.spec.compare: ignore upper 32-bits when pfv.gpr_width=32.
2 years ago
src_a = Signal(self.pfv.gpr_width)
src_b = Signal(self.pfv.gpr_width)
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
result = Record([
("so", 1),
compare: fix incorrect CR bit order. The regression was introduced by b3255def.
2 years ago
("eq_", 1),
("gt", 1),
("lt", 1),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
])
Add checks for CMPRB and CMPEQB instructions.
2 years ago
# Operand A : (RA) or EXTS((RA)(32:63)) or EXTZ((RA)(32:63)) or EXTZ((RA)(56:63))
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
m.d.comb += [
self.pfv.ra.index.eq(self.insn.RA),
self.pfv.ra.r_stb.eq(1),
]
if isinstance(self.insn, (CMPI, CMP)):
with m.If(self.insn.L):
m.d.comb += src_a.eq(self.pfv.ra.r_data)
with m.Else():
m.d.comb += src_a.eq(self.pfv.ra.r_data[:32].as_signed())
elif isinstance(self.insn, (CMPL, CMPLI)):
with m.If(self.insn.L):
m.d.comb += src_a.eq(self.pfv.ra.r_data)
with m.Else():
m.d.comb += src_a.eq(self.pfv.ra.r_data[:32].as_unsigned())
Add checks for CMPRB and CMPEQB instructions.
2 years ago
elif isinstance(self.insn, (CMPRB, CMPEQB)):
m.d.comb += src_a.eq(self.pfv.ra.r_data[:8].as_unsigned())
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
else:
assert False
Add checks for CMPRB and CMPEQB instructions.
2 years ago
# Operand B : SI or UI or (RB) or EXTS((RB)(32:63)) or EXTZ((RB)(32:63))
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
Add checks for CMPRB and CMPEQB instructions.
2 years ago
if isinstance(self.insn, (CMP, CMPL, CMPRB, CMPEQB)):
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
m.d.comb += [
self.pfv.rb.index.eq(self.insn.RB),
self.pfv.rb.r_stb.eq(1),
]
if isinstance(self.insn, CMPI):
m.d.comb += src_b.eq(self.insn.SI)
elif isinstance(self.insn, CMPLI):
m.d.comb += src_b.eq(self.insn.UI)
elif isinstance(self.insn, CMP):
with m.If(self.insn.L):
m.d.comb += src_b.eq(self.pfv.rb.r_data)
with m.Else():
m.d.comb += src_b.eq(self.pfv.rb.r_data[:32].as_signed())
elif isinstance(self.insn, CMPL):
with m.If(self.insn.L):
m.d.comb += src_b.eq(self.pfv.rb.r_data)
with m.Else():
m.d.comb += src_b.eq(self.pfv.rb.r_data[:32].as_unsigned())
Add checks for CMPRB and CMPEQB instructions.
2 years ago
elif isinstance(self.insn, CMPRB):
m.d.comb += src_b.eq(self.pfv.rb.r_data[:32].as_unsigned())
elif isinstance(self.insn, CMPEQB):
m.d.comb += src_b.eq(self.pfv.rb.r_data)
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
else:
assert False
# Result
Add checks for CMPRB and CMPEQB instructions.
2 years ago
if isinstance(self.insn, (CMPI, CMP, CMPLI, CMPL)):
if isinstance(self.insn, (CMPI, CMP)):
m.d.comb += result.lt.eq(src_a.as_signed() < src_b.as_signed())
if isinstance(self.insn, (CMPLI, CMPL)):
m.d.comb += result.lt.eq(src_a.as_unsigned() < src_b.as_unsigned())
m.d.comb += [
result.gt .eq(~(result.lt | result.eq_)),
result.eq_.eq(src_a == src_b),
result.so .eq(self.pfv.xer.r_data.so),
]
elif isinstance(self.insn, CMPRB):
src1 = Signal(unsigned(8))
src21hi = Signal(unsigned(8))
src21lo = Signal(unsigned(8))
src22hi = Signal(unsigned(8))
src22lo = Signal(unsigned(8))
in_range = Signal()
m.d.comb += [
src1.eq(src_a[:8]),
Cat(src22lo, src22hi, src21lo, src21hi).eq(src_b[:32]),
]
with m.If(~self.insn.L):
m.d.comb += in_range.eq( (src22lo <= src1) & (src1 <= src22hi))
with m.Else():
m.d.comb += in_range.eq( (src21lo <= src1) & (src1 <= src21hi)
| (src22lo <= src1) & (src1 <= src22hi))
m.d.comb += result.eq(Cat(Const(0, 2), in_range, Const(0, 1)))
elif isinstance(self.insn, CMPEQB):
_match = 0
insn.spec.compare: ignore upper 32-bits when pfv.gpr_width=32.
2 years ago
for i in range(self.pfv.gpr_width//8):
Add checks for CMPRB and CMPEQB instructions.
2 years ago
_match |= (src_a == src_b.word_select(i, width=8))
m.d.comb += result.eq(Cat(Const(0, 2), _match, Const(0, 1)))
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
else:
assert False
m.d.comb += [
Add checks for CMPRB and CMPEQB instructions.
2 years ago
self.pfv.cr.w_mask.word_select(7-self.insn.BF, width=4).eq(0xf),
self.pfv.cr.w_data.word_select(7-self.insn.BF, width=4).eq(result),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
]
return m