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power-fv/power_fv/insn/spec/cr.py

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In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
from amaranth import *
Add checks for CR Move / Set Boolean instructions.
2 years ago
from amaranth.asserts import Assume
from amaranth.lib.coding import Encoder
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
from power_fv import pfv
from power_fv.insn.const import *
Add checks for CR Move / Set Boolean instructions.
2 years ago
from power_fv.build.sby import SymbiYosysPlatform
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
from . import InsnSpec
from .utils import iea
Add checks for CR Move / Set Boolean instructions.
2 years ago
__all__ = ["CRLogicalSpec", "CRMoveSpec"]
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
Add checks for CR Move / Set Boolean instructions.
2 years ago
class CRLogicalSpec(InsnSpec, Elaboratable):
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
def elaborate(self, platform):
m = Module()
m.d.comb += [
insn: use records to define instruction encodings. Before this commit, instructions were defined by a sequence of Const for fixed fields (e.g. PO/XO) and AnyConst for others (e.g. operands). This approach restricted their use to BMC use-cases, and prevented them from appearing in VCD traces. After this commit, an instruction encoding is defined by a Record. As fields can now be set to arbitrary values, the corresponding InsnSpec will only assert `pfv.stb` if `pfv.insn` matches a valid encoding (i.e. fixed fields have correct values). On the other side, BMC testbenches will drive `pfv.insn` with an AnyConst, and assume `pfv.stb` is high.
2 years ago
self.insn .eq(self.pfv.insn[32:]),
self.pfv.stb .eq(self.insn.is_valid() & ~self.pfv.insn[:32].any()),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
self.pfv.intr.eq(0),
self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
self.pfv.msr.r_mask.sf.eq(1),
]
if isinstance(self.insn, (
CRAND, CROR , CRNAND, CRXOR,
CRNOR, CRANDC, CREQV , CRORC,
)):
src_a = Signal()
src_b = Signal()
result = Signal()
m.d.comb += [
Add checks for CR Move / Set Boolean instructions.
2 years ago
self.pfv.cr.r_mask.bit_select(31-self.insn.BA, width=1).eq(1),
self.pfv.cr.r_mask.bit_select(31-self.insn.BB, width=1).eq(1),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
Add checks for CR Move / Set Boolean instructions.
2 years ago
src_a.eq(self.pfv.cr.r_data.bit_select(31-self.insn.BA, width=1)),
src_b.eq(self.pfv.cr.r_data.bit_select(31-self.insn.BB, width=1)),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
]
if isinstance(self.insn, CRAND):
m.d.comb += result.eq(src_a & src_b)
if isinstance(self.insn, CROR):
m.d.comb += result.eq(src_a | src_b)
if isinstance(self.insn, CRNAND):
m.d.comb += result.eq(~(src_a & src_b))
if isinstance(self.insn, CRXOR):
m.d.comb += result.eq(src_a ^ src_b)
if isinstance(self.insn, CRNOR):
m.d.comb += result.eq(~(src_a | src_b))
if isinstance(self.insn, CRANDC):
m.d.comb += result.eq(src_a & ~src_b)
if isinstance(self.insn, CREQV):
m.d.comb += result.eq(src_a == src_b)
if isinstance(self.insn, CRORC):
m.d.comb += result.eq(src_a | ~src_b)
m.d.comb += [
Add checks for CR Move / Set Boolean instructions.
2 years ago
self.pfv.cr.w_mask.bit_select(31-self.insn.BT, width=1).eq(1),
self.pfv.cr.w_data.bit_select(31-self.insn.BT, width=1).eq(result),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
]
Add checks for CR Move / Set Boolean instructions.
2 years ago
else:
assert False
return m
class CRMoveSpec(InsnSpec, Elaboratable):
def elaborate(self, platform):
m = Module()
m.d.comb += [
insn: use records to define instruction encodings. Before this commit, instructions were defined by a sequence of Const for fixed fields (e.g. PO/XO) and AnyConst for others (e.g. operands). This approach restricted their use to BMC use-cases, and prevented them from appearing in VCD traces. After this commit, an instruction encoding is defined by a Record. As fields can now be set to arbitrary values, the corresponding InsnSpec will only assert `pfv.stb` if `pfv.insn` matches a valid encoding (i.e. fixed fields have correct values). On the other side, BMC testbenches will drive `pfv.insn` with an AnyConst, and assume `pfv.stb` is high.
2 years ago
self.insn .eq(self.pfv.insn[32:]),
self.pfv.stb .eq(self.insn.is_valid() & ~self.pfv.insn[:32].any()),
Add checks for CR Move / Set Boolean instructions.
2 years ago
self.pfv.intr.eq(0),
self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
self.pfv.msr.r_mask.sf.eq(1),
]
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
Add checks for CR Move / Set Boolean instructions.
2 years ago
if isinstance(self.insn, MCRF):
crf = Signal(4)
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
m.d.comb += [
Add checks for CR Move / Set Boolean instructions.
2 years ago
self.pfv.cr.r_mask.word_select(7-self.insn.BFA, width=4).eq(0xf),
crf.eq(self.pfv.cr.r_data.word_select(7-self.insn.BFA, width=4)),
self.pfv.cr.w_mask.word_select(7-self.insn.BF, width=4).eq(0xf),
self.pfv.cr.w_data.word_select(7-self.insn.BF, width=4).eq(crf),
]
elif isinstance(self.insn, MCRXRX):
crf = Record([("ca32", 1), ("ca", 1), ("ov32", 1), ("ov", 1)])
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
Add checks for CR Move / Set Boolean instructions.
2 years ago
m.d.comb += [
self.pfv.xer.r_mask.ov .eq(1),
self.pfv.xer.r_mask.ov32.eq(1),
self.pfv.xer.r_mask.ca .eq(1),
self.pfv.xer.r_mask.ca32.eq(1),
crf.ov .eq(self.pfv.xer.r_data.ov),
crf.ov32.eq(self.pfv.xer.r_data.ov32),
crf.ca .eq(self.pfv.xer.r_data.ca),
crf.ca32.eq(self.pfv.xer.r_data.ca32),
self.pfv.cr.w_mask.word_select(7-self.insn.BF, width=4).eq(0xf),
self.pfv.cr.w_data.word_select(7-self.insn.BF, width=4).eq(crf),
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
]
Add checks for CR Move / Set Boolean instructions.
2 years ago
elif isinstance(self.insn, MTOCRF):
crf = Signal(4)
m.submodules.fxm_enc = fxm_enc = Encoder(width=8)
m.d.comb += [
fxm_enc.i.eq(self.insn.FXM),
self.pfv.rs.index.eq(self.insn.RS),
self.pfv.rs.r_stb.eq(1),
crf.eq(self.pfv.rs.r_data.word_select(fxm_enc.o, width=4)),
self.pfv.cr.w_mask.word_select(fxm_enc.o, width=4).eq(0xf),
self.pfv.cr.w_data.word_select(fxm_enc.o, width=4).eq(crf),
]
# Unless exactly one FXM bit is set to 1, CR contents are undefined.
if isinstance(platform, SymbiYosysPlatform):
m.d.comb += Assume(~fxm_enc.n)
elif isinstance(self.insn, MTCRF):
m.d.comb += [
self.pfv.rs.index.eq(self.insn.RS),
self.pfv.rs.r_stb.eq(1),
self.pfv.cr.w_mask.eq(Cat(Repl(b, 4) for b in self.insn.FXM)),
self.pfv.cr.w_data.eq(self.pfv.rs.r_data[:32]),
]
elif isinstance(self.insn, MFOCRF):
crf = Signal(4)
m.submodules.fxm_enc = fxm_enc = Encoder(width=8)
m.d.comb += [
fxm_enc.i.eq(self.insn.FXM),
self.pfv.cr.r_mask.word_select(fxm_enc.o, width=4).eq(Mux(fxm_enc.n, 0x0, 0xf)),
crf.eq(self.pfv.cr.r_data.word_select(fxm_enc.o, width=4)),
self.pfv.rt.index.eq(self.insn.RT),
self.pfv.rt.w_stb.eq(1),
self.pfv.rt.w_data.word_select(fxm_enc.o, width=4).eq(crf),
]
# Unless exactly one FXM bit is set to 1, RT contents are undefined.
if isinstance(platform, SymbiYosysPlatform):
m.d.comb += Assume(~fxm_enc.n)
elif isinstance(self.insn, MFCR):
m.d.comb += [
self.pfv.cr.r_mask.eq(Repl(1, 32)),
self.pfv.rt.index .eq(self.insn.RT),
self.pfv.rt.w_stb .eq(1),
self.pfv.rt.w_data.eq(self.pfv.cr.r_data),
]
elif isinstance(self.insn, SETB):
crf = Signal(4)
m.d.comb += [
self.pfv.cr.r_mask.word_select(7-self.insn.BFA, width=4).eq(0xf),
crf.eq(self.pfv.cr.r_data.word_select(7-self.insn.BFA, width=4)),
self.pfv.rt.index.eq(self.insn.RT),
self.pfv.rt.w_stb.eq(1),
self.pfv.rt.w_data.eq(Mux(crf[3-0], Repl(1, 64), crf[3-1])),
]
elif isinstance(self.insn, (SETBC, SETBCR, SETNBC, SETNBCR)):
crb = Signal()
m.d.comb += [
self.pfv.cr.r_mask.bit_select(31-self.insn.BI, width=1).eq(1),
crb.eq(self.pfv.cr.r_data.bit_select(31-self.insn.BI, width=1)),
self.pfv.rt.index.eq(self.insn.RT),
self.pfv.rt.w_stb.eq(1),
]
if isinstance(self.insn, SETBC):
m.d.comb += self.pfv.rt.w_data.eq(crb)
if isinstance(self.insn, SETBCR):
m.d.comb += self.pfv.rt.w_data.eq(~crb)
if isinstance(self.insn, SETNBC):
m.d.comb += self.pfv.rt.w_data.eq(Mux(crb, -1, 0))
if isinstance(self.insn, SETNBCR):
m.d.comb += self.pfv.rt.w_data.eq(Mux(crb, 0, -1))
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
else:
assert False
return m