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power-fv/power_fv/pfv.py

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dut: add processor interface.
3 years ago
from amaranth import *
pfv: add ports for IA,GPRs,CR,SPRs and storage.
3 years ago
from amaranth.utils import log2_int
dut: add processor interface.
3 years ago
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
from power_fv.reg import *
dut: add processor interface.
3 years ago
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
__all__ = [
"gprf_port_layout", "reg_port_layout", "mem_port_layout",
"Interface",
]
def gprf_port_layout():
return [
("index" , unsigned( 5)),
("r_stb" , unsigned( 1)),
("r_data", unsigned(64)),
("w_stb", unsigned( 1)),
("w_data", unsigned(64)),
]
def reg_port_layout(reg_layout):
return [
("r_mask", reg_layout),
("r_data", reg_layout),
("w_mask", reg_layout),
("w_data", reg_layout),
]
def mem_port_layout(access):
if access not in ("r", "rw"):
raise ValueError("Access mode must be \"r\" or \"rw\", not {!r}"
.format(access))
granularity = 8
data_width = 64
mask_width = data_width // granularity
addr_width = 64 - log2_int(data_width // granularity)
access_layout = [
("mask", unsigned(mask_width)),
("data", unsigned(data_width)),
]
layout = [("addr", unsigned(addr_width))]
if "r" in access:
layout += [("r", access_layout)]
if "w" in access:
layout += [("w", access_layout)]
return layout
dut: add processor interface.
3 years ago
class Interface(Record):
pfv: add ports for IA,GPRs,CR,SPRs and storage.
3 years ago
"""Power-FV interface.
dut: add processor interface.
3 years ago
The interface between the formal testbench and the processor-under-test.
Attributes
----------
stb : Signal
Instruction strobe. Asserted when the processor retires an instruction. Other signals are
only valid when ``stb`` is asserted.
"""
def __init__(self, *, name=None, src_loc_at=0):
layout = [
In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
("stb" , unsigned( 1)),
("insn" , unsigned(64)),
("order", unsigned(64)),
("intr" , unsigned( 1)),
("cia" , unsigned(64)),
("nia" , unsigned(64)),
("ra", gprf_port_layout()),
("rb", gprf_port_layout()),
("rs", gprf_port_layout()),
("rt", gprf_port_layout()),
("cr" , reg_port_layout( cr_layout)),
("msr" , reg_port_layout( msr_layout)),
("lr" , reg_port_layout( lr_layout)),
("ctr" , reg_port_layout( ctr_layout)),
("tar" , reg_port_layout( tar_layout)),
("xer" , reg_port_layout( xer_layout)),
("srr0", reg_port_layout(srr0_layout)),
("srr1", reg_port_layout(srr1_layout)),
("insn_mem", mem_port_layout(access="r" )),
("data_mem", mem_port_layout(access="rw")),
pfv: add ports for IA,GPRs,CR,SPRs and storage.
3 years ago
]
dut: add processor interface.
3 years ago
super().__init__(layout, name=name, src_loc_at=1 + src_loc_at)