Add checks for Load/Store instructions.
parent
5ca0001b4b
commit
0f731db18a
@ -1,6 +1,7 @@
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from .addsub import *
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from .addsub import *
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from .branch import *
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from .branch import *
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from .cr import *
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from .loadstore import *
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from .compare import *
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from .cr import *
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from .msr import *
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from .compare import *
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from .spr import *
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from .msr import *
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from .spr import *
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@ -0,0 +1,49 @@
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from power_fv.insn import const
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from power_fv.insn.spec.loadstore import LoadStoreSpec
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from power_fv.check.insn import InsnCheck
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__all__ = [
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"LBZ", "LBZX", "LBZU", "LBZUX",
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"LHZ", "LHZX", "LHZU", "LHZUX", "LHA", "LHAX", "LHAU", "LHAUX",
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"LWZ", "LWZU", "LWZX", "LWZUX",
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"STB", "STBX", "STBU", "STBUX",
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"STH", "STHU", "STHX", "STHUX",
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"STW", "STWX", "STWX", "STWUX",
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"LWBRX", "STHBRX", "STWBRX",
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]
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class LBZ (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LBZ ): pass
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class LBZX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LBZX ): pass
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class LBZU (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LBZU ): pass
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class LBZUX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LBZUX): pass
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class LHZ (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHZ ): pass
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class LHZX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHZX ): pass
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class LHZU (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHZU ): pass
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class LHZUX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHZUX): pass
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class LHA (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHA ): pass
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class LHAX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHAX ): pass
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class LHAU (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHAU ): pass
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class LHAUX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LHAUX): pass
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class LWZ (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LWZ ): pass
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class LWZX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LWZX ): pass
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class LWZU (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LWZU ): pass
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class LWZUX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LWZUX): pass
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class STB (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STB ): pass
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class STBX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STBX ): pass
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class STBU (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STBU ): pass
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class STBUX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STBUX): pass
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class STH (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STH ): pass
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class STHX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STHX ): pass
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class STHU (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STHU ): pass
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class STHUX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STHUX): pass
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class STW (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STW ): pass
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class STWX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STWX ): pass
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class STWU (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STWU ): pass
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class STWUX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STWUX): pass
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class LWBRX (InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.LWBRX ): pass
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class STHBRX(InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STHBRX): pass
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class STWBRX(InsnCheck, spec_cls=LoadStoreSpec, insn_cls=const.STWBRX): pass
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@ -0,0 +1,272 @@
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from amaranth import *
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from amaranth.utils import log2_int
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from power_fv import pfv
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from power_fv.insn.const import *
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from . import InsnSpec
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from .utils import iea, byte_reversed
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__all__ = ["LoadStoreSpec"]
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class LoadStoreSpec(InsnSpec, Elaboratable):
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def __init__(self, insn, *, dword_aligned=False):
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self.pfv = pfv.Interface()
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self.insn = insn
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self.dword_aligned = dword_aligned
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def elaborate(self, platform):
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m = Module()
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m.d.comb += [
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self.pfv.stb .eq(1),
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self.pfv.insn.eq(Cat(Const(0, 32), self.insn.as_value())),
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self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
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self.pfv.msr.r_mask.sf.eq(1),
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]
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# EA (effective address) = ea_base + ea_offset
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ea = Signal(64)
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ea_base = Signal(64)
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ea_offset = Signal(64)
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# ea_base : (RA|0) or (RA)
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m.d.comb += self.pfv.ra.index.eq(self.insn.RA)
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if isinstance(self.insn, (
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LBZ, LBZX, LHZ, LHZX, LHA, LHAX, LWZ, LWZX,
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STB, STBX, STH, STHX, STW, STWX,
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LWBRX, STHBRX, STWBRX
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)):
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m.d.comb += [
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self.pfv.ra.r_stb.eq(self.insn.RA != 0),
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ea_base.eq(Mux(self.insn.RA != 0, self.pfv.ra.r_data, 0)),
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]
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elif isinstance(self.insn, (
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LBZU, LBZUX, LHZU, LHZUX, LHAU, LHAUX, LWZU, LWZUX,
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STBU, STBUX, STHU, STHUX, STWU, STWUX
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)):
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m.d.comb += [
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self.pfv.ra.r_stb.eq(1),
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ea_base.eq(self.pfv.ra.r_data),
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]
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else:
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assert False
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# ea_offset : EXTS(D) or (RB)
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if isinstance(self.insn, (
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LBZ, LBZU, LHZ, LHZU, LHA, LHAU, LWZ, LWZU,
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STB, STBU, STH, STHU, STW, STWU,
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)):
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m.d.comb += ea_offset.eq(self.insn.D.as_signed())
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elif isinstance(self.insn, (
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LBZX, LBZUX, LHZX, LHZUX, LHAX, LHAUX, LWZX, LWZUX,
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STBX, STBUX, STHX, STHUX, STWX, STWUX,
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LWBRX, STHBRX, STWBRX,
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)):
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m.d.comb += [
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self.pfv.rb.index.eq(self.insn.RB),
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self.pfv.rb.r_stb.eq(1),
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ea_offset.eq(self.pfv.rb.r_data)
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]
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else:
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assert False
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m.d.comb += ea.eq(iea(ea_base + ea_offset, self.pfv.msr.r_data.sf))
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# If `dword_aligned` is set, `pfv.mem.addr` points to the dword containing EA.
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# If `dword_aligned` is unset, `pfv.mem.addr` is equal to EA.
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byte_offset = Signal(3)
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half_offset = Signal(2)
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word_offset = Signal(1)
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m.d.comb += self.pfv.mem.addr[3:].eq(ea[3:])
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if self.dword_aligned:
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m.d.comb += [
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self.pfv.mem.addr[:3].eq(0),
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byte_offset.eq(ea[:3]),
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]
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else:
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m.d.comb += [
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self.pfv.mem.addr[:3].eq(ea[:3]),
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byte_offset.eq(0),
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]
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m.d.comb += [
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half_offset.eq(byte_offset[1:]),
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word_offset.eq(byte_offset[2:]),
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]
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msr_le = self.pfv.msr.r_data.le
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m.d.comb += self.pfv.msr.r_mask.le.eq(1)
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# Load: read from memory, then write the result to RT.
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if isinstance(self.insn, (
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LBZ, LBZX, LBZU, LBZUX,
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LHZ, LHZX, LHZU, LHZUX,
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LHA, LHAX, LHAU, LHAUX,
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LWZ, LWZX, LWZU, LWZUX,
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LWBRX,
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)):
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load_byte = Signal( 8)
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load_half = Signal(16)
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load_word = Signal(32)
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load_result = Signal(64)
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m.d.comb += [
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load_byte.eq(self.pfv.mem.r_data.word_select(byte_offset, width= 8)),
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load_half.eq(self.pfv.mem.r_data.word_select(half_offset, width=16)),
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load_word.eq(self.pfv.mem.r_data.word_select(word_offset, width=32)),
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]
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if isinstance(self.insn, (LBZ, LBZX, LBZU, LBZUX)):
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m.d.comb += [
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self.pfv.mem.r_mask.word_select(byte_offset, width=1).eq(0x1),
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load_result.eq(load_byte.as_unsigned()),
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]
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elif isinstance(self.insn, (LHZ, LHZX, LHZU, LHZUX)):
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m.d.comb += [
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self.pfv.mem.r_mask.word_select(half_offset, width=2).eq(0x3),
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load_result.eq(byte_reversed(load_half, ~msr_le).as_unsigned()),
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]
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elif isinstance(self.insn, (LHA, LHAX, LHAU, LHAUX)):
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m.d.comb += [
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self.pfv.mem.r_mask.word_select(half_offset, width=2).eq(0x3),
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load_result.eq(byte_reversed(load_half, ~msr_le).as_signed())
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]
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elif isinstance(self.insn, (LWZ, LWZX, LWZU, LWZUX)):
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m.d.comb += [
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self.pfv.mem.r_mask.word_select(word_offset, width=4).eq(0xf),
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load_result.eq(byte_reversed(load_word, ~msr_le).as_unsigned()),
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]
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elif isinstance(self.insn, LWBRX):
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m.d.comb += [
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self.pfv.mem.r_mask.word_select(word_offset, width=4).eq(0xf),
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load_result.eq(byte_reversed(load_word, msr_le).as_unsigned()),
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]
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else:
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assert False
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m.d.comb += [
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self.pfv.rt.index .eq(self.insn.RT),
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self.pfv.rt.w_stb .eq(1),
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self.pfv.rt.w_data.eq(load_result),
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]
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# Store: read from RS, then write the result to memory.
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elif isinstance(self.insn, (
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STB, STBX, STBU, STBUX,
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STH, STHX, STHU, STHUX,
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STW, STWX, STWU, STWUX,
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STHBRX, STWBRX,
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)):
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store_byte = Signal(64)
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store_half = Signal(64)
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store_word = Signal(64)
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m.d.comb += [
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self.pfv.rs.index.eq(self.insn.RS),
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self.pfv.rs.r_stb.eq(1),
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store_byte.eq(Repl(self.pfv.rs.r_data[: 8], count=8)),
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store_half.eq(Repl(self.pfv.rs.r_data[:16], count=4)),
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store_word.eq(Repl(self.pfv.rs.r_data[:32], count=2)),
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]
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if isinstance(self.insn, (STB, STBX, STBU, STBUX)):
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m.d.comb += [
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self.pfv.mem.w_mask.word_select(byte_offset, width=1).eq(0x1),
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self.pfv.mem.w_data.eq(store_byte),
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]
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elif isinstance(self.insn, (STH, STHX, STHU, STHUX)):
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m.d.comb += [
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self.pfv.mem.w_mask.word_select(half_offset, width=2).eq(0x3),
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self.pfv.mem.w_data.eq(byte_reversed(store_half, ~msr_le)),
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]
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elif isinstance(self.insn, (STW, STWX, STWU, STWUX)):
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m.d.comb += [
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self.pfv.mem.w_mask.word_select(word_offset, width=4).eq(0xf),
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self.pfv.mem.w_data.eq(byte_reversed(store_word, ~msr_le)),
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]
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elif isinstance(self.insn, STHBRX):
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m.d.comb += [
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self.pfv.mem.w_mask.word_select(half_offset, width=2).eq(0x3),
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self.pfv.mem.w_data.eq(byte_reversed(store_half, msr_le)),
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]
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elif isinstance(self.insn, STWBRX):
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m.d.comb += [
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self.pfv.mem.w_mask.word_select(word_offset, width=4).eq(0xf),
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self.pfv.mem.w_data.eq(byte_reversed(store_word, msr_le)),
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]
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else:
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assert False
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else:
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assert False
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# Load/store with update: write EA to RA.
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if isinstance(self.insn, (
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LBZU, LBZUX, LHZU, LHZUX, LHAU, LHAUX, LWZU, LWZUX,
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STBU, STBUX, STHU, STHUX, STWU, STWUX,
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)):
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m.d.comb += [
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self.pfv.ra.w_stb .eq(1),
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self.pfv.ra.w_data.eq(ea),
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]
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# Interrupt causes
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intr = Record([
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("misaligned", 1),
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("update_zero", 1),
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("update_rt", 1),
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])
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if isinstance(self.insn, (
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LBZ, LBZX, LBZU, LBZUX,
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STB, STBX, STBU, STBUX,
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)):
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m.d.comb += intr.misaligned.eq(0)
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elif isinstance(self.insn, (
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LHZ, LHZX, LHZU, LHZUX, LHA, LHAX, LHAU, LHAUX,
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STH, STHX, STHU, STHUX,
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STHBRX,
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)):
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m.d.comb += intr.misaligned.eq(byte_offset[0])
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elif isinstance(self.insn, (
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LWZ, LWZX, LWZU, LWZUX,
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STW, STWX, STWU, STWUX,
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LWBRX, STWBRX,
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)):
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m.d.comb += intr.misaligned.eq(byte_offset[:1].any())
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else:
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assert False
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if isinstance(self.insn, (
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LBZU, LBZUX, LHZU, LHZUX, LHAU, LHAUX, LWZU, LWZUX,
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STBU, STBUX, STHU, STHUX, STWU, STWUX,
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)):
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m.d.comb += intr.update_zero.eq(self.insn.RA == 0)
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else:
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m.d.comb += intr.update_zero.eq(0)
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if isinstance(self.insn, (
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LBZU, LBZUX, LHZU, LHZUX, LHAU, LHAUX, LWZU, LWZUX,
|
||||||
|
)):
|
||||||
|
m.d.comb += intr.update_rt.eq(self.insn.RA == self.insn.RT)
|
||||||
|
else:
|
||||||
|
m.d.comb += intr.update_rt.eq(0)
|
||||||
|
|
||||||
|
m.d.comb += self.pfv.intr.eq(intr.any())
|
||||||
|
|
||||||
|
return m
|
||||||
Loading…
Reference in New Issue