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checks.insn._cr: fix order of spec_cr_w_data bits.

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Jean-François Nguyen 3 years ago
parent 010c383ed7
commit 4c16035a70
1 changed files with 1 additions and 1 deletions
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2
power_fv/checks/insn/_cr.py
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@ -87,7 +87,7 @@ class CRSpec(Elaboratable):
spec_cr_r_stb[::-1].bit_select(spec_insn.ba[2:], width=1).eq(1), spec_cr_r_stb[::-1].bit_select(spec_insn.ba[2:], width=1).eq(1),
spec_cr_r_stb[::-1].bit_select(spec_insn.bb[2:], width=1).eq(1), spec_cr_r_stb[::-1].bit_select(spec_insn.bb[2:], width=1).eq(1),
spec_cr_w_stb[::-1].bit_select(spec_insn.bt[2:], width=1).eq(1), spec_cr_w_stb[::-1].bit_select(spec_insn.bt[2:], width=1).eq(1),
spec_cr_w_data.eq(Repl(spec_bt_w_field, 8)) spec_cr_w_data[::-1].eq(Repl(spec_bt_w_field, 8))
] ]
else: else:
assert False assert False

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