Add checks for logical instructions.
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from power_fv.insn import const
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from power_fv.insn.spec.logical import LogicalSpec
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from power_fv.check.insn import InsnCheck
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__all__ = [
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"ANDI_" , "ANDIS_" , "ORI" , "ORIS" , "XORI", "XORIS",
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"AND" , "AND_" , "XOR" , "XOR_" , "NAND", "NAND_",
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"OR" , "OR_" , "ORC" , "ORC_" , "NOR" , "NOR_" ,
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"EQV" , "EQV_" , "ANDC" , "ANDC_" ,
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"EXTSB" , "EXTSB_" , "EXTSH" , "EXTSH_" ,
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"CMPB" ,
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"CNTLZW" , "CNTLZW_", "CNTTZW", "CNTTZW_",
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"POPCNTB", "POPCNTW",
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"PRTYW" ,
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]
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class ANDI_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ANDI_ ): pass
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class ANDIS_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ANDIS_ ): pass
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class ORI (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ORI ): pass
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class ORIS (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ORIS ): pass
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class XORI (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.XORI ): pass
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class XORIS (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.XORIS ): pass
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class AND (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.AND ): pass
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class AND_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.AND_ ): pass
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class XOR (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.XOR ): pass
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class XOR_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.XOR_ ): pass
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class NAND (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.NAND ): pass
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class NAND_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.NAND_ ): pass
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class OR (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.OR ): pass
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class OR_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.OR_ ): pass
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class ORC (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ORC ): pass
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class ORC_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ORC_ ): pass
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class NOR (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.NOR ): pass
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class NOR_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.NOR_ ): pass
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class EQV (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.EQV ): pass
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class EQV_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.EQV_ ): pass
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class ANDC (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ANDC ): pass
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class ANDC_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.ANDC_ ): pass
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class EXTSB (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.EXTSB ): pass
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class EXTSB_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.EXTSB_ ): pass
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class EXTSH (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.EXTSH ): pass
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class EXTSH_ (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.EXTSH_ ): pass
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class CMPB (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.CMPB ): pass
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class CNTLZW (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.CNTLZW ): pass
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class CNTLZW_(InsnCheck, spec_cls=LogicalSpec, insn_cls=const.CNTLZW_): pass
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class CNTTZW (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.CNTTZW ): pass
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class CNTTZW_(InsnCheck, spec_cls=LogicalSpec, insn_cls=const.CNTTZW_): pass
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class POPCNTB(InsnCheck, spec_cls=LogicalSpec, insn_cls=const.POPCNTB): pass
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class POPCNTW(InsnCheck, spec_cls=LogicalSpec, insn_cls=const.POPCNTW): pass
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class PRTYW (InsnCheck, spec_cls=LogicalSpec, insn_cls=const.PRTYW ): pass
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@ -0,0 +1,175 @@
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from amaranth import *
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from amaranth.lib.coding import Encoder
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from power_fv import pfv
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from power_fv.insn.const import *
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from . import InsnSpec
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from .utils import iea
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__all__ = ["LogicalSpec"]
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class _CountTrailingZeros(Elaboratable):
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def __init__(self, width):
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self.width = width
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self.i = Signal(width)
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self.o = Signal(range(width + 1))
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def elaborate(self, platform):
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m = Module()
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m.submodules.lsb_enc = lsb_enc = Encoder(self.width)
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m.d.comb += [
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lsb_enc.i.eq(self.i & -self.i),
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self.o.eq(Mux(lsb_enc.n, self.width, lsb_enc.o)),
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]
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return m
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class LogicalSpec(InsnSpec, Elaboratable):
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def __init__(self, insn):
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self.pfv = pfv.Interface()
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self.insn = insn
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def elaborate(self, platform):
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m = Module()
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m.d.comb += [
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self.pfv.stb .eq(1),
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self.pfv.insn.eq(Cat(Const(0, 32), self.insn.as_value())),
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self.pfv.intr.eq(0),
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self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
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self.pfv.msr.r_mask.sf.eq(1),
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]
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src_a = Signal(unsigned(64))
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src_b = Signal(unsigned(64))
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# Operand A : (RS)
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m.d.comb += [
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self.pfv.rs.index.eq(self.insn.RS),
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self.pfv.rs.r_stb.eq(1),
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src_a.eq(self.pfv.rs.r_data),
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]
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# Operand B : EXTZ(UI) or EXTZ(UI<<16) or (RB)
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if isinstance(self.insn, (ANDI_, ORI, XORI)):
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m.d.comb += src_b.eq(self.insn.UI)
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elif isinstance(self.insn, (ANDIS_, ORIS, XORIS)):
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m.d.comb += src_b.eq(Cat(Const(0, 16), self.insn.UI).as_unsigned())
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elif isinstance(self.insn, (
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AND , AND_, XOR , XOR_ , NAND, NAND_,
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OR , OR_ , ORC , ORC_ , NOR , NOR_ ,
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EQV , EQV_, ANDC, ANDC_,
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CMPB,
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)):
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m.d.comb += [
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self.pfv.rb.index.eq(self.insn.RB),
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self.pfv.rb.r_stb.eq(1),
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src_b.eq(self.pfv.rb.r_data),
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]
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elif isinstance(self.insn, (
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EXTSB , EXTSB_ , EXTSH , EXTSH_ ,
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CNTLZW , CNTLZW_, CNTTZW, CNTTZW_,
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POPCNTB, POPCNTW, PRTYW ,
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)):
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pass
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else:
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assert False
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result = Signal(64)
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if isinstance(self.insn, (ANDI_, ANDIS_, AND, AND_)):
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m.d.comb += result.eq(src_a & src_b)
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elif isinstance(self.insn, (ORI, ORIS, OR, OR_)):
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m.d.comb += result.eq(src_a | src_b)
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elif isinstance(self.insn, (XORI, XORIS, XOR, XOR_)):
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m.d.comb += result.eq(src_a ^ src_b)
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elif isinstance(self.insn, (NAND, NAND_)):
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m.d.comb += result.eq(~(src_a & src_b))
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elif isinstance(self.insn, (ORC, ORC_)):
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m.d.comb += result.eq(src_a | ~src_b)
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elif isinstance(self.insn, (NOR, NOR_)):
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m.d.comb += result.eq(~(src_a | src_b))
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elif isinstance(self.insn, (EQV, EQV_)):
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m.d.comb += result.eq(~(src_a ^ src_b))
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elif isinstance(self.insn, (ANDC, ANDC_)):
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m.d.comb += result.eq(src_a & ~src_b)
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elif isinstance(self.insn, (EXTSB, EXTSB_)):
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m.d.comb += result.eq(src_a[: 8].as_signed())
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elif isinstance(self.insn, (EXTSH, EXTSH_)):
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m.d.comb += result.eq(src_a[:16].as_signed())
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elif isinstance(self.insn, CMPB):
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for i in range(64//8):
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a_byte = src_a .word_select(i, width=8)
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b_byte = src_b .word_select(i, width=8)
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r_byte = result.word_select(i, width=8)
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m.d.comb += r_byte.eq(Mux(a_byte == b_byte, 0xff, 0x00))
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elif isinstance(self.insn, (CNTLZW, CNTLZW_, CNTTZW, CNTTZW_)):
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m.submodules.cnttz = cnttz = _CountTrailingZeros(width=32)
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if isinstance(self.insn, (CNTTZW, CNTTZW_)):
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m.d.comb += cnttz.i.eq(src_a[:32])
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if isinstance(self.insn, (CNTLZW, CNTLZW_)):
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m.d.comb += cnttz.i.eq(Cat(reversed(src_a[:32])))
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m.d.comb += result.eq(cnttz.o)
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elif isinstance(self.insn, POPCNTB):
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for i in range(64//8):
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a_byte = src_a .word_select(i, width=8)
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r_byte = result.word_select(i, width=8)
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m.d.comb += r_byte.eq(sum(a_bit for a_bit in a_byte))
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elif isinstance(self.insn, POPCNTW):
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for i in range(64//32):
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a_word = src_a .word_select(i, width=32)
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r_word = result.word_select(i, width=32)
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m.d.comb += r_word.eq(sum(a_bit for a_bit in a_word))
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elif isinstance(self.insn, PRTYW):
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prty_lo = 0
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prty_hi = 0
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for i in range(32//8):
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prty_lo ^= src_a[i*8]
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prty_hi ^= src_a[i*8 + 32]
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m.d.comb += result.eq(Cat(prty_lo, Const(0, 31), prty_hi, Const(0, 31)))
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else:
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assert False
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# Write result to RA
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m.d.comb += [
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self.pfv.ra.index .eq(self.insn.RA),
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self.pfv.ra.w_stb .eq(1),
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self.pfv.ra.w_data.eq(result),
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]
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# Write CR0
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if isinstance(self.insn, (
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ANDI_, ANDIS_, AND_, XOR_, NAND_, OR_, ORC_, NOR_, EQV_, ANDC_,
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EXTSB_, EXTSH_, CNTLZW_, CNTTZW_,
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)):
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cr0_w_mask = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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cr0_w_data = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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m.d.comb += [
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self.pfv.xer.r_mask.so.eq(1),
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cr0_w_mask .eq(0b1111),
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cr0_w_data.so .eq(self.pfv.xer.r_data.so),
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cr0_w_data.eq_.eq(~Mux(self.pfv.msr.r_data.sf, result[:64].any(), result[:32].any())),
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cr0_w_data.gt .eq(~(cr0_w_data.lt | cr0_w_data.eq_)),
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cr0_w_data.lt .eq(Mux(self.pfv.msr.r_data.sf, result[63], result[31])),
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self.pfv.cr.w_mask.cr0.eq(cr0_w_mask),
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self.pfv.cr.w_data.cr0.eq(cr0_w_data),
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]
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return m
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