cores/microwatt: expose MSR and SRR0/SRR1.

cores/microwatt/_wrapper.py

@@ -145,6 +145,21 @@ class MicrowattWrapper(Elaboratable):
             ("o", "pfv_tar_r_data", self.pfv.tar.r_data),
             ("o", "pfv_tar_w_stb",  self.pfv.tar.w_stb),
             ("o", "pfv_tar_w_data", self.pfv.tar.w_data),
+
+            ("o", "pfv_srr0_r_stb",  self.pfv.srr0.r_stb),
+            ("o", "pfv_srr0_r_data", self.pfv.srr0.r_data),
+            ("o", "pfv_srr0_w_stb",  self.pfv.srr0.w_stb),
+            ("o", "pfv_srr0_w_data", self.pfv.srr0.w_data),
+
+            ("o", "pfv_srr1_r_stb",  self.pfv.srr1.r_stb),
+            ("o", "pfv_srr1_r_data", self.pfv.srr1.r_data),
+            ("o", "pfv_srr1_w_stb",  self.pfv.srr1.w_stb),
+            ("o", "pfv_srr1_w_data", self.pfv.srr1.w_data),
+
+            ("o", "pfv_msr_r_stb",  self.pfv.msr.r_stb),
+            ("o", "pfv_msr_r_data", self.pfv.msr.r_data),
+            ("o", "pfv_msr_w_stb",  self.pfv.msr.w_stb),
+            ("o", "pfv_msr_w_data", self.pfv.msr.w_data),
         )
 
         with m.If(Initial()):

cores/microwatt/microwatt_top.vhdl

@@ -82,7 +82,22 @@ entity toplevel is
         pfv_tar_r_stb  : out std_ulogic;
         pfv_tar_r_data : out std_ulogic_vector(63 downto 0);
         pfv_tar_w_stb  : out std_ulogic;
-        pfv_tar_w_data : out std_ulogic_vector(63 downto 0)
+        pfv_tar_w_data : out std_ulogic_vector(63 downto 0);
+
+        pfv_srr0_r_stb  : out std_ulogic;
+        pfv_srr0_r_data : out std_ulogic_vector(63 downto 0);
+        pfv_srr0_w_stb  : out std_ulogic;
+        pfv_srr0_w_data : out std_ulogic_vector(63 downto 0);
+
+        pfv_srr1_r_stb  : out std_ulogic;
+        pfv_srr1_r_data : out std_ulogic_vector(63 downto 0);
+        pfv_srr1_w_stb  : out std_ulogic;
+        pfv_srr1_w_data : out std_ulogic_vector(63 downto 0);
+
+        pfv_msr_r_stb  : out std_ulogic;
+        pfv_msr_r_data : out std_ulogic_vector(63 downto 0);
+        pfv_msr_w_stb  : out std_ulogic;
+        pfv_msr_w_data : out std_ulogic_vector(63 downto 0)
         );
 end entity toplevel;
 
@@ -176,4 +191,19 @@ begin
         pfv_tar_w_stb  <= pfv.tar.w_stb;
         pfv_tar_w_data <= pfv.tar.w_data;
 
+        pfv_srr0_r_stb  <= pfv.srr0.r_stb;
+        pfv_srr0_r_data <= pfv.srr0.r_data;
+        pfv_srr0_w_stb  <= pfv.srr0.w_stb;
+        pfv_srr0_w_data <= pfv.srr0.w_data;
+
+        pfv_srr1_r_stb  <= pfv.srr1.r_stb;
+        pfv_srr1_r_data <= pfv.srr1.r_data;
+        pfv_srr1_w_stb  <= pfv.srr1.w_stb;
+        pfv_srr1_w_data <= pfv.srr1.w_data;
+
+        pfv_msr_r_stb  <= pfv.msr.r_stb;
+        pfv_msr_r_data <= pfv.msr.r_data;
+        pfv_msr_w_stb  <= pfv.msr.w_stb;
+        pfv_msr_w_data <= pfv.msr.w_data;
+
 end architecture behave;