pfv: add MSR and SRR0/SRR1 SPRs.

3 years ago · c6a74333e8
parent 58bef1a741
commit c6a74333e8
1 changed files with 3 additions and 0 deletions
--- a/power_fv/pfv.py
+++ b/power_fv/pfv.py
@ -79,6 +79,9 @@ class Interface(Record):
                "ctr",
                "tar",
                "xer",
+                "srr0",
+                "srr1",
+                "msr",
            )
        ]