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pfv: add MSR and SRR0/SRR1 SPRs.

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Jean-François Nguyen 3 years ago
parent 58bef1a741
commit c6a74333e8
1 changed files with 3 additions and 0 deletions
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power_fv/pfv.py
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@ -79,6 +79,9 @@ class Interface(Record):
"ctr", "ctr",
"tar", "tar",
"xer", "xer",
"srr0",
"srr1",
"msr",
) )
] ]



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