check.insn: ignore upper SPR 32-bits when pfv.gpr_width=32.

main
Jean-François Nguyen 2 years ago
parent d687a9a511
commit e30ea40a8b

@ -215,8 +215,9 @@ class _MemPortTest(Elaboratable):


class _SysRegTest(Elaboratable): class _SysRegTest(Elaboratable):
def __init__(self, check, *, reg): def __init__(self, check, *, reg):
self._dut = getattr(check.dut .pfv, reg) self._dut = getattr(check.dut .pfv, reg)
self._spec = getattr(check.spec.pfv, reg) self._spec = getattr(check.spec.pfv, reg)
self._width = check.dut.pfv.gpr_width


self.valid = Record([ self.valid = Record([
("read" , [("r_mask", 1)]), ("read" , [("r_mask", 1)]),
@ -238,6 +239,7 @@ class _SysRegTest(Elaboratable):
]) ])


def contains(a, mask, b=None): def contains(a, mask, b=None):
mask &= 2**self._width - 1
if b is None: if b is None:
b = mask b = mask
return a & mask == b & mask return a & mask == b & mask

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