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276 lines
9.1 KiB
Python
276 lines
9.1 KiB
Python
from amaranth import *
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from power_fv import pfv
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from power_fv.insn.const import *
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from . import InsnSpec
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from .utils import iea
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__all__ = ["AddSubSpec"]
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class AddSubSpec(InsnSpec, Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.d.comb += [
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self.insn .eq(self.pfv.insn[32:]),
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self.pfv.stb .eq(self.insn.is_valid() & ~self.pfv.insn[:32].any()),
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self.pfv.intr.eq(0),
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self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
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self.pfv.msr.r_mask.sf.eq(1),
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]
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src_a = Signal(signed(64))
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src_b = Signal(signed(64))
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src_c = Signal()
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result = Signal(unsigned(65))
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ca_64 = Signal()
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ca_32 = Signal()
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ov_64 = Signal()
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ov_32 = Signal()
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# Operand A : (RA) or 0 or NIA or ~(RA)
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if isinstance(self.insn, (ADDI, ADDIS)):
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m.d.comb += [
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self.pfv.ra.index.eq(self.insn.RA),
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self.pfv.ra.r_stb.eq(self.insn.RA != 0),
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src_a.eq(Mux(self.insn.RA != 0, self.pfv.ra.r_data, 0)),
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]
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elif isinstance(self.insn, ADDPCIS):
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m.d.comb += src_a.eq(self.pfv.nia)
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elif isinstance(self.insn, (
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ADD , ADD_ , ADDO , ADDO_ ,
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ADDIC, ADDIC_,
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ADDC , ADDC_ , ADDCO , ADDCO_ ,
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ADDE , ADDE_ , ADDEO , ADDEO_ ,
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ADDME, ADDME_, ADDMEO, ADDMEO_,
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ADDZE, ADDZE_, ADDZEO, ADDZEO_,
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ADDEX,
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)):
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m.d.comb += [
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self.pfv.ra.index.eq(self.insn.RA),
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self.pfv.ra.r_stb.eq(1),
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src_a.eq(self.pfv.ra.r_data),
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]
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elif isinstance(self.insn, (
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SUBF , SUBF_ , SUBFO , SUBFO_ ,
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SUBFIC,
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SUBFC , SUBFC_ , SUBFCO , SUBFCO_ ,
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SUBFE , SUBFE_ , SUBFEO , SUBFEO_ ,
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SUBFME, SUBFME_, SUBFMEO, SUBFMEO_,
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SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_,
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NEG , NEG_ , NEGO , NEGO_ ,
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)):
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m.d.comb += [
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self.pfv.ra.index.eq(self.insn.RA),
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self.pfv.ra.r_stb.eq(1),
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src_a.eq(~self.pfv.ra.r_data),
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]
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else:
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assert False
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# Operand B : SI or SI<<16 or D<<16 or (RB) or -1 or 0
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if isinstance(self.insn, (ADDI, ADDIC, ADDIC_, SUBFIC)):
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m.d.comb += src_b.eq(self.insn.SI)
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elif isinstance(self.insn, ADDIS):
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m.d.comb += src_b.eq(Cat(Const(0, 16), self.insn.SI).as_signed())
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elif isinstance(self.insn, ADDPCIS):
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imm_d = Signal(signed(16))
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m.d.comb += [
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imm_d.eq(Cat(self.insn.d2, self.insn.d1, self.insn.d0)),
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src_b.eq(Cat(Const(0, 16), imm_d).as_signed()),
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]
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elif isinstance(self.insn, (
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ADD , ADD_ , ADDO , ADDO_ ,
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SUBF , SUBF_ , SUBFO , SUBFO_ ,
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ADDC , ADDC_ , ADDCO , ADDCO_ ,
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ADDE , ADDE_ , ADDEO , ADDEO_ ,
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SUBFC, SUBFC_, SUBFCO, SUBFCO_,
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SUBFE, SUBFE_, SUBFEO, SUBFEO_,
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ADDEX,
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)):
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m.d.comb += [
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self.pfv.rb.index.eq(self.insn.RB),
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self.pfv.rb.r_stb.eq(1),
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src_b.eq(self.pfv.rb.r_data),
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]
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elif isinstance(self.insn, (
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ADDME , ADDME_ , ADDMEO , ADDMEO_ ,
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SUBFME, SUBFME_, SUBFMEO, SUBFMEO_,
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)):
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m.d.comb += src_b.eq(-1)
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elif isinstance(self.insn, (
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ADDZE , ADDZE_ , ADDZEO , ADDZEO_ ,
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SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_,
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NEG , NEG_ , NEGO , NEGO_ ,
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)):
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m.d.comb += src_b.eq(0)
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else:
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assert False
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# Operand C : 0 or 1 or XER.CA or XER.OV
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if isinstance(self.insn, (
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ADDI , ADDIS , ADDPCIS,
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ADD , ADD_ , ADDO , ADDO_ ,
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ADDIC, ADDIC_,
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ADDC , ADDC_ , ADDCO , ADDCO_,
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)):
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m.d.comb += src_c.eq(0)
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elif isinstance(self.insn, (
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SUBF , SUBF_ , SUBFO , SUBFO_ ,
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SUBFIC,
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SUBFC , SUBFC_, SUBFCO, SUBFCO_,
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NEG , NEG_ , NEGO , NEGO_ ,
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)):
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m.d.comb += src_c.eq(1)
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elif isinstance(self.insn, (
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ADDE , ADDE_ , ADDEO , ADDEO_ ,
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SUBFE , SUBFE_ , SUBFEO , SUBFEO_ ,
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ADDME , ADDME_ , ADDMEO , ADDMEO_ ,
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ADDZE , ADDZE_ , ADDZEO , ADDZEO_ ,
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SUBFME, SUBFME_, SUBFMEO, SUBFMEO_,
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SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_,
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)):
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m.d.comb += [
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self.pfv.xer.r_mask.ca.eq(1),
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src_c.eq(self.pfv.xer.r_data.ca),
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]
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elif isinstance(self.insn, ADDEX):
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m.d.comb += [
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self.pfv.xer.r_mask.ov.eq(1),
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src_c.eq(self.pfv.xer.r_data.ov),
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]
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else:
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assert False
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# Result : Operand A + Operand B + Operand C
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src_a_zext = Signal(unsigned(65))
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src_b_zext = Signal(unsigned(65))
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result = Signal(unsigned(65))
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m.d.comb += [
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src_a_zext.eq(src_a.as_unsigned()),
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src_b_zext.eq(src_b.as_unsigned()),
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result.eq(src_a_zext + src_b_zext + src_c),
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ca_64.eq(result[64]),
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ca_32.eq(result[32] ^ src_a[32] ^ src_b[32]),
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ov_64.eq((ca_64 ^ result[63]) & ~(src_a[63] ^ src_b[63])),
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ov_32.eq((ca_32 ^ result[31]) & ~(src_a[31] ^ src_b[31])),
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self.pfv.rt.index .eq(self.insn.RT),
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self.pfv.rt.w_stb .eq(1),
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self.pfv.rt.w_data.eq(result[:64]),
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]
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# Read XER.SO (to update CR0)
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if isinstance(self.insn, (
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ADD_ , ADDO_ , ADDIC_ ,
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SUBF_ , SUBFO_ ,
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ADDC_ , ADDCO_ , ADDE_ , ADDEO_ ,
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SUBFC_ , SUBFCO_ , SUBFE_ , SUBFEO_ ,
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ADDME_ , ADDMEO_ , ADDZE_ , ADDZEO_ ,
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SUBFME_, SUBFMEO_, SUBFZE_, SUBFZEO_,
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NEG_ , NEGO_ ,
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)):
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m.d.comb += self.pfv.xer.r_mask.so.eq(1)
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# Write XER.SO, XER.OV and XER.OV32
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if isinstance(self.insn, (
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ADDO , ADDO_ , SUBFO , SUBFO_ ,
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ADDCO , ADDCO_ , SUBFCO , SUBFCO_ ,
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ADDEO , ADDEO_ , SUBFEO , SUBFEO_ ,
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ADDMEO, ADDMEO_, SUBFMEO, SUBFMEO_,
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ADDZEO, ADDZEO_, SUBFZEO, SUBFZEO_,
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NEGO , NEGO_ ,
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)):
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m.d.comb += [
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self.pfv.xer.w_mask.ov .eq(1),
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self.pfv.xer.w_data.ov .eq(Mux(self.pfv.msr.r_data.sf, ov_64, ov_32)),
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self.pfv.xer.w_mask.ov32.eq(1),
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self.pfv.xer.w_data.ov32.eq(ov_32),
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]
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with m.If(self.pfv.xer.w_data.ov):
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m.d.comb += [
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self.pfv.xer.w_mask.so.eq(1),
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self.pfv.xer.w_data.so.eq(1),
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]
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elif isinstance(self.insn, ADDEX):
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m.d.comb += [
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self.pfv.xer.w_mask.ov .eq(1),
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self.pfv.xer.w_data.ov .eq(Mux(self.pfv.msr.r_data.sf, ca_64, ca_32)),
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self.pfv.xer.w_mask.ov32.eq(1),
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self.pfv.xer.w_data.ov32.eq(ca_32),
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]
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# Write XER.CA and XER.CA32
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if isinstance(self.insn, (
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ADDIC , ADDIC_ , SUBFIC ,
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ADDC , ADDC_ , ADDCO , ADDCO_ ,
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SUBFC , SUBFC_ , SUBFCO , SUBFCO_ ,
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ADDE , ADDE_ , ADDEO , ADDEO_ ,
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SUBFE , SUBFE_ , SUBFEO , SUBFEO_ ,
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ADDME , ADDME_ , ADDMEO , ADDMEO_ ,
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SUBFME, SUBFME_, SUBFMEO, SUBFMEO_,
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ADDZE , ADDZE_ , ADDZEO , ADDZEO_ ,
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SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_,
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)):
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m.d.comb += [
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self.pfv.xer.w_mask.ca .eq(1),
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self.pfv.xer.w_data.ca .eq(Mux(self.pfv.msr.r_data.sf, ca_64, ca_32)),
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self.pfv.xer.w_mask.ca32.eq(1),
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self.pfv.xer.w_data.ca32.eq(ca_32),
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]
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# Write CR0
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if isinstance(self.insn, (
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ADD_ , ADDO_ , ADDIC_ ,
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SUBF_ , SUBFO_ ,
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ADDC_ , ADDCO_ , ADDE_ , ADDEO_ ,
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SUBFC_ , SUBFCO_ , SUBFE_ , SUBFEO_ ,
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ADDME_ , ADDMEO_ , ADDZE_ , ADDZEO_ ,
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SUBFME_, SUBFMEO_, SUBFZE_, SUBFZEO_,
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NEG_ , NEGO_ ,
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)):
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cr0_w_mask = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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cr0_w_data = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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m.d.comb += [
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cr0_w_mask .eq(0b1111),
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cr0_w_data.so .eq(Mux(self.pfv.xer.w_mask.so, self.pfv.xer.w_data.so, self.pfv.xer.r_data.so)),
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cr0_w_data.eq_.eq(~Mux(self.pfv.msr.r_data.sf, result[:64].any(), result[:32].any())),
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cr0_w_data.gt .eq(~(cr0_w_data.lt | cr0_w_data.eq_)),
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cr0_w_data.lt .eq(Mux(self.pfv.msr.r_data.sf, result[63], result[31])),
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self.pfv.cr.w_mask.cr0.eq(cr0_w_mask),
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self.pfv.cr.w_data.cr0.eq(cr0_w_data),
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]
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return m
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