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Make core testbenches recognized by VUnit

Browse Source 
This commit also removes the dependencies these testbenches have on VHPIDIRECT.
The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using
foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists.
For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions.

The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using
the -p option to the run.py script

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
remove-potato-uart
Lars Asplund 4 years ago
parent 41d57e6148
commit 08c0c4c1b4
10 changed files with 182 additions and 103 deletions
Show Stats Download Patch File Download Diff File

1
.github/workflows/test.yml vendored
Unescape Escape View File

@ -33,7 +33,6 @@ jobs:
max-parallel: 3 max-parallel: 3
matrix: matrix:
task: [ task: [
"tests_unit",
"tests_console", "tests_console",
"{1..99}", "{1..99}",
"{100..199}", "{100..199}",

16
Makefile
Unescape Escape View File

@ -39,8 +39,8 @@ ECPPACK = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
OPENOCD = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd OPENOCD = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd
endif endif


all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \ all = core_tb icache_tb dcache_tb dmi_dtm_tb \
rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb wishbone_bram_tb soc_reset_tb


all: $(all) all: $(all)


@ -62,7 +62,7 @@ uart_files = $(wildcard uart16550/*.v)
soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \ soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \ sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
sim_16550_uart.vhdl \ sim_16550_uart.vhdl \
random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl foreign_random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl


soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \ soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
sim_jtag_socket_c.c sim_jtag_socket_c.c
@ -79,7 +79,6 @@ $(unisim_lib): $(unisim_lib_files)
$(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^ $(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
GHDLFLAGS += -P$(unisim_dir) GHDLFLAGS += -P$(unisim_dir)


core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
soc_flash_tbs = core_flash_tb soc_flash_tbs = core_flash_tb
soc_dram_tbs = dram_tb core_dram_tb soc_dram_tbs = dram_tb core_dram_tb
@ -105,9 +104,6 @@ $(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_l
$(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl $(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
$(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@ $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@


$(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
$(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@

soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
$(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@ $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@


@ -236,19 +232,15 @@ test_micropython: core_tb
test_micropython_long: core_tb test_micropython_long: core_tb
@./scripts/test_micropython_long.py @./scripts/test_micropython_long.py


tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs)) tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))


%_test: % %_test: %
./$< --assert-level=error > /dev/null ./$< --assert-level=error > /dev/null


tests_core: $(tests_core_tb)

tests_soc: $(tests_soc_tb) tests_soc: $(tests_soc_tb)


# FIXME SOC tests have bit rotted, so disable for now # FIXME SOC tests have bit rotted, so disable for now
#tests_unit: tests_core tests_soc #tests_unit: tests_soc
tests_unit: tests_core


TAGS: TAGS:
find . -name '*.vhdl' | xargs ./scripts/vhdltags find . -name '*.vhdl' | xargs ./scripts/vhdltags

19
countzero_tb.vhdl
Unescape Escape View File

@ -1,12 +1,18 @@
library vunit_lib;
context vunit_lib.vunit_context;

library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;


library work; library work;
use work.common.all; use work.common.all;
use work.glibc_random.all;
library osvvm;
use osvvm.RandomPkg.all;


entity countzero_tb is entity countzero_tb is
generic (runner_cfg : string := runner_cfg_default);
end countzero_tb; end countzero_tb;


architecture behave of countzero_tb is architecture behave of countzero_tb is
@ -37,7 +43,12 @@ begin


stim_process: process stim_process: process
variable r: std_ulogic_vector(63 downto 0); variable r: std_ulogic_vector(63 downto 0);
variable rnd : RandomPType;
begin begin
rnd.InitSeed(stim_process'path_name);

test_runner_setup(runner, runner_cfg);

-- test with input = 0 -- test with input = 0
report "test zero input"; report "test zero input";
rs <= (others => '0'); rs <= (others => '0');
@ -63,7 +74,7 @@ begin
report "test cntlzd/w"; report "test cntlzd/w";
count_right <= '0'; count_right <= '0';
for j in 0 to 100 loop for j in 0 to 100 loop
r := pseudorand(64); r := rnd.RandSlv(64);
r(63) := '1'; r(63) := '1';
for i in 0 to 63 loop for i in 0 to 63 loop
rs <= r; rs <= r;
@ -88,7 +99,7 @@ begin
report "test cnttzd/w"; report "test cnttzd/w";
count_right <= '1'; count_right <= '1';
for j in 0 to 100 loop for j in 0 to 100 loop
r := pseudorand(64); r := rnd.RandSlv(64);
r(0) := '1'; r(0) := '1';
for i in 0 to 63 loop for i in 0 to 63 loop
rs <= r; rs <= r;
@ -109,6 +120,6 @@ begin
end loop; end loop;
end loop; end loop;


std.env.finish; test_runner_cleanup(runner);
end process; end process;
end behave; end behave;

63
divider_tb.vhdl
Unescape Escape View File

@ -1,3 +1,6 @@
library vunit_lib;
context vunit_lib.vunit_context;

library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@ -5,10 +8,13 @@ use ieee.numeric_std.all;
library work; library work;
use work.decode_types.all; use work.decode_types.all;
use work.common.all; use work.common.all;
use work.glibc_random.all;
use work.ppc_fx_insns.all; use work.ppc_fx_insns.all;


library osvvm;
use osvvm.RandomPkg.all;

entity divider_tb is entity divider_tb is
generic (runner_cfg : string := runner_cfg_default);
end divider_tb; end divider_tb;


architecture behave of divider_tb is architecture behave of divider_tb is
@ -37,7 +43,12 @@ begin
variable q128: std_ulogic_vector(127 downto 0); variable q128: std_ulogic_vector(127 downto 0);
variable q64: std_ulogic_vector(63 downto 0); variable q64: std_ulogic_vector(63 downto 0);
variable rem32: std_ulogic_vector(31 downto 0); variable rem32: std_ulogic_vector(31 downto 0);
variable rnd : RandomPType;
begin begin
rnd.InitSeed(stim_process'path_name);

test_runner_setup(runner, runner_cfg);

rst <= '1'; rst <= '1';
wait for clk_period; wait for clk_period;
rst <= '0'; rst <= '0';
@ -94,8 +105,8 @@ begin
divd_loop : for dlength in 1 to 8 loop divd_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra)); d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
@ -129,8 +140,8 @@ begin
divdu_loop : for dlength in 1 to 8 loop divdu_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
@ -164,8 +175,8 @@ begin
divde_loop : for vlength in 1 to 8 loop divde_loop : for vlength in 1 to 8 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra)); d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
@ -205,8 +216,8 @@ begin
divdeu_loop : for vlength in 1 to 8 loop divdeu_loop : for vlength in 1 to 8 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
@ -243,8 +254,8 @@ begin
divw_loop : for dlength in 1 to 4 loop divw_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra)); d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
@ -280,8 +291,8 @@ begin
divwu_loop : for dlength in 1 to 4 loop divwu_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
@ -317,8 +328,8 @@ begin
divwe_loop : for vlength in 1 to 4 loop divwe_loop : for vlength in 1 to 4 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 32)) & x"00000000"; ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 32)) & x"00000000";
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra)); d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
@ -358,8 +369,8 @@ begin
divweu_loop : for vlength in 1 to 4 loop divweu_loop : for vlength in 1 to 4 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 32)) & x"00000000"; ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 32)) & x"00000000";
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
@ -395,8 +406,8 @@ begin
modsd_loop : for dlength in 1 to 8 loop modsd_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra)); d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
@ -433,8 +444,8 @@ begin
modud_loop : for dlength in 1 to 8 loop modud_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
@ -471,8 +482,8 @@ begin
modsw_loop : for dlength in 1 to 4 loop modsw_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra)); d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
@ -514,8 +525,8 @@ begin
moduw_loop : for dlength in 1 to 4 loop moduw_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64)); ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64)); rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
@ -547,6 +558,6 @@ begin
end loop; end loop;
end loop; end loop;


std.env.finish; test_runner_cleanup(runner);
end process; end process;
end behave; end behave;

30
foreign_random.vhdl
Unescape Escape View File

@ -0,0 +1,30 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.glibc_random.all;

entity random is
port (
clk : in std_ulogic;
data : out std_ulogic_vector(63 downto 0);
raw : out std_ulogic_vector(63 downto 0);
err : out std_ulogic
);
end entity random;

architecture behaviour of random is
begin
err <= '0';

process(clk)
variable rand : std_ulogic_vector(63 downto 0);
begin
if rising_edge(clk) then
rand := pseudorand(64);
data <= rand;
raw <= rand;
end if;
end process;
end behaviour;

43
multiply_tb.vhdl
Unescape Escape View File

@ -1,3 +1,6 @@
library vunit_lib;
context vunit_lib.vunit_context;

library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@ -5,10 +8,13 @@ use ieee.numeric_std.all;
library work; library work;
use work.decode_types.all; use work.decode_types.all;
use work.common.all; use work.common.all;
use work.glibc_random.all;
use work.ppc_fx_insns.all; use work.ppc_fx_insns.all;


library osvvm;
use osvvm.RandomPkg.all;

entity multiply_tb is entity multiply_tb is
generic (runner_cfg : string := runner_cfg_default);
end multiply_tb; end multiply_tb;


architecture behave of multiply_tb is architecture behave of multiply_tb is
@ -46,7 +52,12 @@ begin
variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0); variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
variable si: std_ulogic_vector(15 downto 0); variable si: std_ulogic_vector(15 downto 0);
variable sign: std_ulogic; variable sign: std_ulogic;
variable rnd : RandomPType;
begin begin
rnd.InitSeed(stim_process'path_name);

test_runner_setup(runner, runner_cfg);

wait for clk_period; wait for clk_period;


m1.valid <= '1'; m1.valid <= '1';
@ -84,8 +95,8 @@ begin


-- test mulld -- test mulld
mulld_loop : for i in 0 to 1000 loop mulld_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := rnd.RandSlv(ra'length);
rb := pseudorand(rb'length); rb := rnd.RandSlv(rb'length);


behave_rt := ppc_mulld(ra, rb); behave_rt := ppc_mulld(ra, rb);


@ -110,8 +121,8 @@ begin


-- test mulhdu -- test mulhdu
mulhdu_loop : for i in 0 to 1000 loop mulhdu_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := rnd.RandSlv(ra'length);
rb := pseudorand(rb'length); rb := rnd.RandSlv(rb'length);


behave_rt := ppc_mulhdu(ra, rb); behave_rt := ppc_mulhdu(ra, rb);


@ -135,8 +146,8 @@ begin


-- test mulhd -- test mulhd
mulhd_loop : for i in 0 to 1000 loop mulhd_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := rnd.RandSlv(ra'length);
rb := pseudorand(rb'length); rb := rnd.RandSlv(rb'length);


behave_rt := ppc_mulhd(ra, rb); behave_rt := ppc_mulhd(ra, rb);


@ -161,8 +172,8 @@ begin


-- test mullw -- test mullw
mullw_loop : for i in 0 to 1000 loop mullw_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := rnd.RandSlv(ra'length);
rb := pseudorand(rb'length); rb := rnd.RandSlv(rb'length);


behave_rt := ppc_mullw(ra, rb); behave_rt := ppc_mullw(ra, rb);


@ -189,8 +200,8 @@ begin


-- test mulhw -- test mulhw
mulhw_loop : for i in 0 to 1000 loop mulhw_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := rnd.RandSlv(ra'length);
rb := pseudorand(rb'length); rb := rnd.RandSlv(rb'length);


behave_rt := ppc_mulhw(ra, rb); behave_rt := ppc_mulhw(ra, rb);


@ -218,8 +229,8 @@ begin


-- test mulhwu -- test mulhwu
mulhwu_loop : for i in 0 to 1000 loop mulhwu_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := rnd.RandSlv(ra'length);
rb := pseudorand(rb'length); rb := rnd.RandSlv(rb'length);


behave_rt := ppc_mulhwu(ra, rb); behave_rt := ppc_mulhwu(ra, rb);


@ -246,8 +257,8 @@ begin


-- test mulli -- test mulli
mulli_loop : for i in 0 to 1000 loop mulli_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := rnd.RandSlv(ra'length);
si := pseudorand(si'length); si := rnd.RandSlv(si'length);


behave_rt := ppc_mulli(ra, si); behave_rt := ppc_mulli(ra, si);


@ -271,7 +282,7 @@ begin
report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0)); report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0));
end loop; end loop;


std.env.finish; test_runner_cleanup(runner);
wait; wait;
end process; end process;
end behave; end behave;

8
plru_tb.vhdl
Unescape Escape View File

@ -1,3 +1,6 @@
library vunit_lib;
context vunit_lib.vunit_context;

library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;


@ -6,6 +9,7 @@ use work.common.all;
use work.wishbone_types.all; use work.wishbone_types.all;


entity plru_tb is entity plru_tb is
generic (runner_cfg : string := runner_cfg_default);
end plru_tb; end plru_tb;


architecture behave of plru_tb is architecture behave of plru_tb is
@ -50,6 +54,8 @@ begin


stim: process stim: process
begin begin
test_runner_setup(runner, runner_cfg);

wait for 4*clk_period; wait for 4*clk_period;


report "accessing 1:"; report "accessing 1:";
@ -103,6 +109,6 @@ begin
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


std.env.finish; test_runner_cleanup(runner);
end process; end process;
end; end;

7
random.vhdl
Unescape Escape View File

@ -2,8 +2,8 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;


library work; library osvvm;
use work.glibc_random.all; use osvvm.RandomPkg.all;


entity random is entity random is
port ( port (
@ -20,9 +20,10 @@ begin


process(clk) process(clk)
variable rand : std_ulogic_vector(63 downto 0); variable rand : std_ulogic_vector(63 downto 0);
variable rnd : RandomPType;
begin begin
if rising_edge(clk) then if rising_edge(clk) then
rand := pseudorand(64); rand := rnd.RandSlv(64);
data <= rand; data <= rand;
raw <= rand; raw <= rand;
end if; end if;

83
rotator_tb.vhdl
Unescape Escape View File

@ -1,14 +1,20 @@
library vunit_lib;
context vunit_lib.vunit_context;

library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;


library work; library work;
use work.common.all; use work.common.all;
use work.glibc_random.all;
use work.ppc_fx_insns.all; use work.ppc_fx_insns.all;
use work.insn_helpers.all; use work.insn_helpers.all;


library osvvm;
use osvvm.RandomPkg.all;

entity rotator_tb is entity rotator_tb is
generic (runner_cfg : string := runner_cfg_default);
end rotator_tb; end rotator_tb;


architecture behave of rotator_tb is architecture behave of rotator_tb is
@ -41,7 +47,12 @@ begin
stim_process: process stim_process: process
variable behave_ra: std_ulogic_vector(63 downto 0); variable behave_ra: std_ulogic_vector(63 downto 0);
variable behave_ca_ra: std_ulogic_vector(64 downto 0); variable behave_ca_ra: std_ulogic_vector(64 downto 0);
variable rnd : RandomPType;
begin begin
rnd.InitSeed(stim_process'path_name);

test_runner_setup(runner, runner_cfg);

-- rlwinm, rlwnm -- rlwinm, rlwnm
report "test rlw[i]nm"; report "test rlw[i]nm";
ra <= (others => '0'); ra <= (others => '0');
@ -52,9 +63,9 @@ begin
clear_right <= '1'; clear_right <= '1';
extsw <= '0'; extsw <= '0';
rlwnm_loop : for i in 0 to 1000 loop rlwnm_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
assert behave_ra = result assert behave_ra = result
@ -69,10 +80,10 @@ begin
clear_left <= '1'; clear_left <= '1';
clear_right <= '1'; clear_right <= '1';
rlwimi_loop : for i in 0 to 1000 loop rlwimi_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
ra <= pseudorand(64); ra <= rnd.RandSlv(64);
shift <= "00" & pseudorand(5); shift <= "00" & rnd.RandSlv(5);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
assert behave_ra = result assert behave_ra = result
@ -88,9 +99,9 @@ begin
clear_left <= '1'; clear_left <= '1';
clear_right <= '0'; clear_right <= '0';
rldicl_loop : for i in 0 to 1000 loop rldicl_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result assert behave_ra = result
@ -106,9 +117,9 @@ begin
clear_left <= '0'; clear_left <= '0';
clear_right <= '1'; clear_right <= '1';
rldicr_loop : for i in 0 to 1000 loop rldicr_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn)); behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
--report "rs = " & to_hstring(rs); --report "rs = " & to_hstring(rs);
@ -129,9 +140,9 @@ begin
clear_left <= '1'; clear_left <= '1';
clear_right <= '1'; clear_right <= '1';
rldic_loop : for i in 0 to 1000 loop rldic_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= '0' & pseudorand(6); shift <= '0' & rnd.RandSlv(6);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result assert behave_ra = result
@ -146,10 +157,10 @@ begin
clear_left <= '1'; clear_left <= '1';
clear_right <= '1'; clear_right <= '1';
rldimi_loop : for i in 0 to 1000 loop rldimi_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
ra <= pseudorand(64); ra <= rnd.RandSlv(64);
shift <= '0' & pseudorand(6); shift <= '0' & rnd.RandSlv(6);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result assert behave_ra = result
@ -165,8 +176,8 @@ begin
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
slw_loop : for i in 0 to 1000 loop slw_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
@ -182,8 +193,8 @@ begin
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
sld_loop : for i in 0 to 1000 loop sld_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
@ -199,8 +210,8 @@ begin
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
srw_loop : for i in 0 to 1000 loop srw_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
@ -216,8 +227,8 @@ begin
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
srd_loop : for i in 0 to 1000 loop srd_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
@ -233,8 +244,8 @@ begin
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
sraw_loop : for i in 0 to 1000 loop sraw_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= '0' & pseudorand(6); shift <= '0' & rnd.RandSlv(6);
wait for clk_period; wait for clk_period;
behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
--report "rs = " & to_hstring(rs); --report "rs = " & to_hstring(rs);
@ -254,8 +265,8 @@ begin
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
srad_loop : for i in 0 to 1000 loop srad_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= pseudorand(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
--report "rs = " & to_hstring(rs); --report "rs = " & to_hstring(rs);
@ -276,8 +287,8 @@ begin
clear_right <= '0'; clear_right <= '0';
extsw <= '1'; extsw <= '1';
extswsli_loop : for i in 0 to 1000 loop extswsli_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= rnd.RandSlv(64);
shift <= '0' & pseudorand(6); shift <= '0' & rnd.RandSlv(6);
wait for clk_period; wait for clk_period;
behave_ra := rs; behave_ra := rs;
behave_ra(63 downto 32) := (others => rs(31)); behave_ra(63 downto 32) := (others => rs(31));
@ -291,6 +302,6 @@ begin
report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


std.env.finish; test_runner_cleanup(runner);
end process; end process;
end behave; end behave;

15
run.py
Unescape Escape View File

@ -3,16 +3,23 @@ from vunit import VUnit
from glob import glob from glob import glob


prj = VUnit.from_argv() prj = VUnit.from_argv()
prj.add_osvvm()
root = Path(__file__).parent root = Path(__file__).parent


lib = prj.add_library("lib") lib = prj.add_library("lib")
lib.add_source_files(root / "litedram/extras/*.vhdl") lib.add_source_files(root / "litedram/extras/*.vhdl")
lib.add_source_files(root / "litedram/generated/sim/*.vhdl") lib.add_source_files(root / "litedram/generated/sim/*.vhdl")


# Use multiply.vhd and not xilinx-mult.vhd # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
vhdl_files_in_root = glob(str(root / "*.vhdl")) vhdl_files = glob(str(root / "*.vhdl"))
vhdl_files_to_use = [src_file for src_file in vhdl_files_in_root if "xilinx-mult" not in src_file] vhdl_files = [
lib.add_source_files(vhdl_to_use) src_file
for src_file in vhdl_files
if ("xilinx-mult" not in src_file)
and ("foreign_random" not in src_file)
and ("nonrandom" not in src_file)
]
lib.add_source_files(vhdl_files)


unisim = prj.add_library("unisim") unisim = prj.add_library("unisim")
unisim.add_source_files(root / "sim-unisim/*.vhdl") unisim.add_source_files(root / "sim-unisim/*.vhdl")

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