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@ -1,6 +1,9 @@
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GHDL ?= ghdl
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GHDLFLAGS=--std=08 -frelaxed
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GHDLFLAGS=--std=08
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CFLAGS=-O3 -Wall
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VERILATOR_FLAGS=-O3
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# It takes forever to build with optimisation, so disable by default
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#VERILATOR_CFLAGS=-O3
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GHDLSYNTH ?= ghdl.so
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YOSYS ?= yosys
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@ -50,13 +53,13 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
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loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
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core.vhdl fpu.vhdl
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soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
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soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
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wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
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spi_rxtx.vhdl spi_flash_ctrl.vhdl
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uart_files = $(wildcard uart16550/*.v)
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soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
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soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
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sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
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sim_16550_uart.vhdl \
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random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
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@ -115,8 +118,6 @@ $(soc_dram_tbs):
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$(error "Verilator is required to make this target !")
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else
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VERILATOR_CFLAGS=-O3
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VERILATOR_FLAGS=-O3
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verilated_dram: litedram/generated/sim/litedram_core.v
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verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
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make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
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@ -126,7 +127,7 @@ SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -fa
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sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
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$(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
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soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
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soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
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soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
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soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
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dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
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@ -184,7 +185,7 @@ CLK_FREQUENCY=50000000
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clkgen=fpga/clk_gen_bypass.vhd
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endif
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fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
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fpga_files = fpga/soc_reset.vhdl \
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fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
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nonrandom.vhdl
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@ -198,7 +199,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
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# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
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microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
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verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
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verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
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make -C obj_dir -f Vmicrowatt.mk
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@cp -f obj_dir/microwatt-verilator microwatt-verilator
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