Merge pull request #333 from ozbenh/wukong

Add support for  QMTech Wukong v2 board

fpga/clk_gen_plle2.vhd

@@ -70,6 +70,18 @@ architecture rtl of clock_generator is
                 report "Unsupported output frequency" severity failure;
                 return bad_settings;
             end case;
+        when 50000000 =>
+            case output_hz is
+            when 100000000 =>
+                return (clkin_period  => 20.0,
+                        clkfbout_mult => 32,
+                        clkout_divide => 16,
+                        divclk_divide => 1,
+                        force_rst     => '0');
+            when others =>
+                report "Unsupported output frequency" severity failure;
+                return bad_settings;
+            end case;
         when others =>
             report "Unsupported input frequency" severity failure;
             return bad_settings;

fpga/top-wukong-v2.vhdl

@@ -0,0 +1,579 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity toplevel is
+    generic (
+        MEMORY_SIZE        : integer  := 16384;
+        RAM_INIT_FILE      : string   := "firmware.hex";
+        RESET_LOW          : boolean  := true;
+        CLK_FREQUENCY      : positive := 100000000;
+        HAS_FPU            : boolean  := true;
+        HAS_BTC            : boolean  := true;
+        HAS_SHORT_MULT     : boolean  := false;
+        USE_LITEDRAM       : boolean  := false;
+        NO_BRAM            : boolean  := false;
+        DISABLE_FLATTEN_CORE : boolean := false;
+        SPI_FLASH_OFFSET   : integer := 4194304;
+        SPI_FLASH_DEF_CKDV : natural := 1;
+        SPI_FLASH_DEF_QUAD : boolean := true;
+        LOG_LENGTH         : natural := 512;
+        USE_LITEETH        : boolean  := false;
+        UART_IS_16550      : boolean  := true;
+        HAS_UART1          : boolean  := false;
+        USE_LITESDCARD     : boolean := false;
+        HAS_GPIO           : boolean := false;
+        NGPIO              : natural := 32
+        );
+    port(
+        ext_clk   : in  std_ulogic;
+        ext_rst_n : in  std_ulogic;
+
+        -- UART0 signals:
+        uart_main_tx : out std_ulogic;
+        uart_main_rx : in  std_ulogic;
+
+        -- LEDs
+        led0_n  : out std_ulogic;
+        led1_n  : out std_ulogic;
+
+        -- SPI
+        spi_flash_cs_n   : out std_ulogic;
+        spi_flash_mosi   : inout std_ulogic;
+        spi_flash_miso   : inout std_ulogic;
+        spi_flash_wp_n   : inout std_ulogic;
+        spi_flash_hold_n : inout std_ulogic;
+
+        -- Ethernet
+        eth_clocks_tx    : in std_ulogic;
+        eth_clocks_gtx   : out std_ulogic;
+        eth_clocks_rx    : in std_ulogic;
+        eth_rst_n        : out std_ulogic;
+        eth_mdio         : inout std_ulogic;
+        eth_mdc          : out std_ulogic;
+        eth_rx_dv        : in std_ulogic;
+        eth_rx_er        : in std_ulogic;
+        eth_rx_data      : in std_ulogic_vector(7 downto 0);
+        eth_tx_en        : out std_ulogic;
+        eth_tx_er        : out std_ulogic;
+        eth_tx_data      : out std_ulogic_vector(7 downto 0);
+        eth_col          : in std_ulogic;
+        eth_crs          : in std_ulogic;
+
+        -- SD card
+        sdcard_data   : inout std_ulogic_vector(3 downto 0);
+        sdcard_cmd    : inout std_ulogic;
+        sdcard_clk    : out   std_ulogic;
+        sdcard_cd     : in    std_ulogic;
+
+        -- DRAM wires
+        ddram_a       : out std_ulogic_vector(13 downto 0);
+        ddram_ba      : out std_ulogic_vector(2 downto 0);
+        ddram_ras_n   : out std_ulogic;
+        ddram_cas_n   : out std_ulogic;
+        ddram_we_n    : out std_ulogic;
+        ddram_dm      : out std_ulogic_vector(1 downto 0);
+        ddram_dq      : inout std_ulogic_vector(15 downto 0);
+        ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+        ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+        ddram_clk_p   : out std_ulogic;
+        ddram_clk_n   : out std_ulogic;
+        ddram_cke     : out std_ulogic;
+        ddram_odt     : out std_ulogic;
+        ddram_reset_n : out std_ulogic
+        );
+end entity toplevel;
+
+architecture behaviour of toplevel is
+
+    -- Reset signals:
+    signal soc_rst : std_ulogic;
+    signal pll_rst : std_ulogic;
+
+    -- Internal clock signals:
+    signal system_clk        : std_ulogic;
+    signal system_clk_locked : std_ulogic;
+
+    -- External IOs from the SoC
+    signal wb_ext_io_in        : wb_io_master_out;
+    signal wb_ext_io_out       : wb_io_slave_out;
+    signal wb_ext_is_dram_csr  : std_ulogic;
+    signal wb_ext_is_dram_init : std_ulogic;
+    signal wb_ext_is_eth       : std_ulogic;
+    signal wb_ext_is_sdcard    : std_ulogic;
+
+    -- DRAM main data wishbone connection
+    signal wb_dram_in          : wishbone_master_out;
+    signal wb_dram_out         : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_dram_ctrl_out    : wb_io_slave_out := wb_io_slave_out_init;
+
+    -- LiteEth connection
+    signal ext_irq_eth         : std_ulogic;
+    signal wb_eth_out          : wb_io_slave_out := wb_io_slave_out_init;
+
+    -- LiteSDCard connection
+    signal ext_irq_sdcard      : std_ulogic := '0';
+    signal wb_sdcard_out       : wb_io_slave_out := wb_io_slave_out_init;
+    signal wb_sddma_out        : wb_io_master_out := wb_io_master_out_init;
+    signal wb_sddma_in         : wb_io_slave_out;
+    signal wb_sddma_nr         : wb_io_master_out;
+    signal wb_sddma_ir         : wb_io_slave_out;
+    -- for conversion from non-pipelined wishbone to pipelined
+    signal wb_sddma_stb_sent   : std_ulogic;
+
+    -- Control/status
+    signal core_alt_reset : std_ulogic;
+
+    -- SPI flash
+    signal spi_sck     : std_ulogic;
+    signal spi_cs_n    : std_ulogic;
+    signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
+
+    -- Fixup various memory sizes based on generics
+    function get_bram_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return 0;
+        else
+            return MEMORY_SIZE;
+        end if;
+    end function;
+
+    function get_payload_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return MEMORY_SIZE;
+        else
+            return 0;
+        end if;
+    end function;
+    
+    constant BRAM_SIZE    : natural := get_bram_size;
+    constant PAYLOAD_SIZE : natural := get_payload_size;
+begin
+
+    -- Main SoC
+    soc0: entity work.soc
+        generic map(
+            MEMORY_SIZE        => BRAM_SIZE,
+            RAM_INIT_FILE      => RAM_INIT_FILE,
+            SIM                => false,
+            CLK_FREQ           => CLK_FREQUENCY,
+            HAS_FPU            => HAS_FPU,
+            HAS_BTC            => HAS_BTC,
+            HAS_SHORT_MULT     => HAS_SHORT_MULT,
+            HAS_DRAM           => USE_LITEDRAM,
+            DRAM_SIZE          => 256 * 1024 * 1024,
+            DRAM_INIT_SIZE     => PAYLOAD_SIZE,
+            DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
+            HAS_SPI_FLASH      => true,
+            SPI_FLASH_DLINES   => 4,
+            SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
+            SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
+            SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
+            LOG_LENGTH         => LOG_LENGTH,
+            HAS_LITEETH        => USE_LITEETH,
+            UART0_IS_16550     => UART_IS_16550,
+            HAS_UART1          => HAS_UART1,
+            HAS_SD_CARD        => USE_LITESDCARD,
+            HAS_GPIO           => HAS_GPIO,
+            NGPIO              => NGPIO
+            )
+        port map (
+            -- System signals
+            system_clk        => system_clk,
+            rst               => soc_rst,
+
+            -- UART signals
+            uart0_txd         => uart_main_tx,
+            uart0_rxd         => uart_main_rx,
+
+            -- SPI signals
+            spi_flash_sck     => spi_sck,
+            spi_flash_cs_n    => spi_cs_n,
+            spi_flash_sdat_o  => spi_sdat_o,
+            spi_flash_sdat_oe => spi_sdat_oe,
+            spi_flash_sdat_i  => spi_sdat_i,
+
+            -- External interrupts
+            ext_irq_eth       => ext_irq_eth,
+            ext_irq_sdcard    => ext_irq_sdcard,
+
+            -- DRAM wishbone
+            wb_dram_in           => wb_dram_in,
+            wb_dram_out          => wb_dram_out,
+
+            -- IO wishbone
+            wb_ext_io_in         => wb_ext_io_in,
+            wb_ext_io_out        => wb_ext_io_out,
+            wb_ext_is_dram_csr   => wb_ext_is_dram_csr,
+            wb_ext_is_dram_init  => wb_ext_is_dram_init,
+            wb_ext_is_eth        => wb_ext_is_eth,
+            wb_ext_is_sdcard     => wb_ext_is_sdcard,
+
+            -- DMA wishbone
+            wishbone_dma_in      => wb_sddma_in,
+            wishbone_dma_out     => wb_sddma_out,
+
+            alt_reset            => core_alt_reset
+            );
+
+    -- SPI Flash
+    spi_flash_cs_n   <= spi_cs_n;
+    spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
+    spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
+    spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
+    spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
+    spi_sdat_i(0)    <= spi_flash_mosi;
+    spi_sdat_i(1)    <= spi_flash_miso;
+    spi_sdat_i(2)    <= spi_flash_wp_n;
+    spi_sdat_i(3)    <= spi_flash_hold_n;
+
+    STARTUPE2_INST: STARTUPE2
+        port map (
+            CLK => '0',
+            GSR => '0',
+            GTS => '0',
+            KEYCLEARB => '0',
+            PACK => '0',
+            USRCCLKO => spi_sck,
+            USRCCLKTS => '0',
+            USRDONEO => '1',
+            USRDONETS => '0'
+            );
+
+    nodram: if not USE_LITEDRAM generate
+        signal ddram_clk_dummy : std_ulogic;
+    begin
+        reset_controller: entity work.soc_reset
+            generic map(
+                RESET_LOW => RESET_LOW
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_clk => system_clk,
+                pll_locked_in => system_clk_locked,
+                ext_rst_in => ext_rst_n,
+                pll_rst_out => pll_rst,
+                rst_out => soc_rst
+                );
+
+        clkgen: entity work.clock_generator
+            generic map(
+                CLK_INPUT_HZ => 50000000,
+                CLK_OUTPUT_HZ => CLK_FREQUENCY
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_rst_in => pll_rst,
+                pll_clk_out => system_clk,
+                pll_locked_out => system_clk_locked
+                );
+
+        core_alt_reset <= '0';
+
+        -- Vivado barfs on those differential signals if left
+        -- unconnected. So instanciate a diff. buffer and feed
+        -- it a constant '0'.
+        dummy_dram_clk: OBUFDS
+            port map (
+                O => ddram_clk_p,
+                OB => ddram_clk_n,
+                I => ddram_clk_dummy
+                );
+        ddram_clk_dummy <= '0';
+
+    end generate;
+
+    has_dram: if USE_LITEDRAM generate
+        signal dram_init_done  : std_ulogic;
+        signal dram_init_error : std_ulogic;
+        signal dram_sys_rst    : std_ulogic;
+        signal rst_gen_rst     : std_ulogic;
+    begin
+
+        -- Eventually dig out the frequency from the generator
+        -- but for now, assert it's 100Mhz
+        assert CLK_FREQUENCY = 100000000;
+
+        reset_controller: entity work.soc_reset
+            generic map(
+                RESET_LOW => RESET_LOW,
+                PLL_RESET_BITS => 18,
+                SOC_RESET_BITS => 1
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_clk => system_clk,
+                pll_locked_in => system_clk_locked,
+                ext_rst_in => ext_rst_n,
+                pll_rst_out => pll_rst,
+                rst_out => rst_gen_rst
+                );
+
+        -- Generate SoC reset
+        soc_rst_gen: process(system_clk)
+        begin
+            if ext_rst_n = '0' then
+                soc_rst <= '1';
+            elsif rising_edge(system_clk) then
+                soc_rst <= dram_sys_rst or not system_clk_locked;
+            end if;
+        end process;
+
+        dram: entity work.litedram_wrapper
+            generic map(
+                DRAM_ABITS => 24,
+                DRAM_ALINES => 14,
+                DRAM_DLINES => 16,
+                DRAM_PORT_WIDTH => 128,
+                PAYLOAD_FILE => RAM_INIT_FILE,
+                PAYLOAD_SIZE => PAYLOAD_SIZE
+                )
+            port map(
+                clk_in          => ext_clk,
+                rst             => pll_rst,
+                system_clk      => system_clk,
+                system_reset    => dram_sys_rst,
+                core_alt_reset  => core_alt_reset,
+                pll_locked      => system_clk_locked,
+
+                wb_in           => wb_dram_in,
+                wb_out          => wb_dram_out,
+                wb_ctrl_in      => wb_ext_io_in,
+                wb_ctrl_out     => wb_dram_ctrl_out,
+                wb_ctrl_is_csr  => wb_ext_is_dram_csr,
+                wb_ctrl_is_init => wb_ext_is_dram_init,
+
+                init_done       => dram_init_done,
+                init_error      => dram_init_error,
+
+                ddram_a         => ddram_a,
+                ddram_ba        => ddram_ba,
+                ddram_ras_n     => ddram_ras_n,
+                ddram_cas_n     => ddram_cas_n,
+                ddram_we_n      => ddram_we_n,
+		ddram_cs_n	=> open,
+                ddram_dm        => ddram_dm,
+                ddram_dq        => ddram_dq,
+                ddram_dqs_p     => ddram_dqs_p,
+                ddram_dqs_n     => ddram_dqs_n,
+                ddram_clk_p     => ddram_clk_p,
+                ddram_clk_n     => ddram_clk_n,
+                ddram_cke       => ddram_cke,
+                ddram_odt       => ddram_odt,
+                ddram_reset_n   => ddram_reset_n
+                );
+
+    end generate;
+
+    has_liteeth : if USE_LITEETH generate
+
+        component liteeth_core port (
+            sys_clock           : in std_ulogic;
+            sys_reset           : in std_ulogic;
+            gmii_eth_clocks_tx  : in std_ulogic;
+            gmii_eth_clocks_gtx : out std_ulogic;
+            gmii_eth_clocks_rx  : in std_ulogic;
+            gmii_eth_rst_n      : out std_ulogic;
+            gmii_eth_mdio       : inout std_ulogic;
+            gmii_eth_mdc        : out std_ulogic;
+            gmii_eth_rx_dv      : in std_ulogic;
+            gmii_eth_rx_er      : in std_ulogic;
+            gmii_eth_rx_data    : in std_ulogic_vector(7 downto 0);
+            gmii_eth_tx_en      : out std_ulogic;
+            gmii_eth_tx_er      : out std_ulogic;
+            gmii_eth_tx_data    : out std_ulogic_vector(7 downto 0);
+            gmii_eth_col        : in std_ulogic;
+            gmii_eth_crs        : in std_ulogic;
+            wishbone_adr        : in std_ulogic_vector(29 downto 0);
+            wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
+            wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
+            wishbone_sel        : in std_ulogic_vector(3 downto 0);
+            wishbone_cyc        : in std_ulogic;
+            wishbone_stb        : in std_ulogic;
+            wishbone_ack        : out std_ulogic;
+            wishbone_we         : in std_ulogic;
+            wishbone_cti        : in std_ulogic_vector(2 downto 0);
+            wishbone_bte        : in std_ulogic_vector(1 downto 0);
+            wishbone_err        : out std_ulogic;
+            interrupt           : out std_ulogic
+            );
+        end component;
+
+        signal wb_eth_cyc     : std_ulogic;
+        signal wb_eth_adr     : std_ulogic_vector(29 downto 0);
+
+        -- Change this to use a PLL instead of a BUFR to generate the 25Mhz
+        -- reference clock to the PHY.
+        constant USE_PLL : boolean := false;
+    begin
+        liteeth :  liteeth_core
+            port map(
+                sys_clock           => system_clk,
+                sys_reset           => soc_rst,
+                gmii_eth_clocks_tx  => eth_clocks_tx,
+                gmii_eth_clocks_gtx => eth_clocks_gtx,
+                gmii_eth_clocks_rx  => eth_clocks_rx,
+                gmii_eth_rst_n      => eth_rst_n,
+                gmii_eth_mdio       => eth_mdio,
+                gmii_eth_mdc        => eth_mdc,
+                gmii_eth_rx_dv      => eth_rx_dv,
+                gmii_eth_rx_er      => eth_rx_er,
+                gmii_eth_rx_data    => eth_rx_data,
+                gmii_eth_tx_en      => eth_tx_en,
+                gmii_eth_tx_er      => eth_tx_er,
+                gmii_eth_tx_data    => eth_tx_data,
+                gmii_eth_col        => eth_col,
+                gmii_eth_crs        => eth_crs,
+                wishbone_adr        => wb_eth_adr,
+                wishbone_dat_w      => wb_ext_io_in.dat,
+                wishbone_dat_r      => wb_eth_out.dat,
+                wishbone_sel        => wb_ext_io_in.sel,
+                wishbone_cyc        => wb_eth_cyc,
+                wishbone_stb        => wb_ext_io_in.stb,
+                wishbone_ack        => wb_eth_out.ack,
+                wishbone_we         => wb_ext_io_in.we,
+                wishbone_cti        => "000",
+                wishbone_bte        => "00",
+                wishbone_err        => open,
+                interrupt           => ext_irq_eth
+                );
+
+        -- Gate cyc with "chip select" from soc
+        wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
+
+        -- Remove top address bits as liteeth decoder doesn't know about them
+        wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0);
+
+        -- LiteETH isn't pipelined
+        wb_eth_out.stall <= not wb_eth_out.ack;
+
+    end generate;
+
+    no_liteeth : if not USE_LITEETH generate
+        ext_irq_eth    <= '0';
+    end generate;
+
+    -- SD card pmod
+    has_sdcard : if USE_LITESDCARD generate
+        component litesdcard_core port (
+            clk           : in    std_ulogic;
+            rst           : in    std_ulogic;
+            -- wishbone for accessing control registers
+            wb_ctrl_adr   : in    std_ulogic_vector(29 downto 0);
+            wb_ctrl_dat_w : in    std_ulogic_vector(31 downto 0);
+            wb_ctrl_dat_r : out   std_ulogic_vector(31 downto 0);
+            wb_ctrl_sel   : in    std_ulogic_vector(3 downto 0);
+            wb_ctrl_cyc   : in    std_ulogic;
+            wb_ctrl_stb   : in    std_ulogic;
+            wb_ctrl_ack   : out   std_ulogic;
+            wb_ctrl_we    : in    std_ulogic;
+            wb_ctrl_cti   : in    std_ulogic_vector(2 downto 0);
+            wb_ctrl_bte   : in    std_ulogic_vector(1 downto 0);
+            wb_ctrl_err   : out   std_ulogic;
+            -- wishbone for SD card core to use for DMA
+            wb_dma_adr    : out   std_ulogic_vector(29 downto 0);
+            wb_dma_dat_w  : out   std_ulogic_vector(31 downto 0);
+            wb_dma_dat_r  : in    std_ulogic_vector(31 downto 0);
+            wb_dma_sel    : out   std_ulogic_vector(3 downto 0);
+            wb_dma_cyc    : out   std_ulogic;
+            wb_dma_stb    : out   std_ulogic;
+            wb_dma_ack    : in    std_ulogic;
+            wb_dma_we     : out   std_ulogic;
+            wb_dma_cti    : out   std_ulogic_vector(2 downto 0);
+            wb_dma_bte    : out   std_ulogic_vector(1 downto 0);
+            wb_dma_err    : in    std_ulogic;
+            -- connections to SD card
+            sdcard_data   : inout std_ulogic_vector(3 downto 0);
+            sdcard_cmd    : inout std_ulogic;
+            sdcard_clk    : out   std_ulogic;
+            sdcard_cd     : in    std_ulogic;
+            irq           : out   std_ulogic
+            );
+        end component;
+
+        signal wb_sdcard_cyc : std_ulogic;
+        signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
+
+    begin
+        litesdcard : litesdcard_core
+            port map (
+                clk           => system_clk,
+                rst           => soc_rst,
+                wb_ctrl_adr   => wb_sdcard_adr,
+                wb_ctrl_dat_w => wb_ext_io_in.dat,
+                wb_ctrl_dat_r => wb_sdcard_out.dat,
+                wb_ctrl_sel   => wb_ext_io_in.sel,
+                wb_ctrl_cyc   => wb_sdcard_cyc,
+                wb_ctrl_stb   => wb_ext_io_in.stb,
+                wb_ctrl_ack   => wb_sdcard_out.ack,
+                wb_ctrl_we    => wb_ext_io_in.we,
+                wb_ctrl_cti   => "000",
+                wb_ctrl_bte   => "00",
+                wb_ctrl_err   => open,
+                wb_dma_adr    => wb_sddma_nr.adr,
+                wb_dma_dat_w  => wb_sddma_nr.dat,
+                wb_dma_dat_r  => wb_sddma_ir.dat,
+                wb_dma_sel    => wb_sddma_nr.sel,
+                wb_dma_cyc    => wb_sddma_nr.cyc,
+                wb_dma_stb    => wb_sddma_nr.stb,
+                wb_dma_ack    => wb_sddma_ir.ack,
+                wb_dma_we     => wb_sddma_nr.we,
+                wb_dma_cti    => open,
+                wb_dma_bte    => open,
+                wb_dma_err    => '0',
+                sdcard_data   => sdcard_data,
+                sdcard_cmd    => sdcard_cmd,
+                sdcard_clk    => sdcard_clk,
+                sdcard_cd     => sdcard_cd,
+                irq           => ext_irq_sdcard
+                );
+
+        -- Gate cyc with chip select from SoC
+        wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
+
+        wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
+
+        wb_sdcard_out.stall <= not wb_sdcard_out.ack;
+
+        -- Convert non-pipelined DMA wishbone to pipelined by suppressing
+        -- non-acknowledged strobes
+        process(system_clk)
+        begin
+            if rising_edge(system_clk) then
+                wb_sddma_out <= wb_sddma_nr;
+                if wb_sddma_stb_sent = '1' or
+                    (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
+                    wb_sddma_out.stb <= '0';
+                end if;
+                if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
+                    wb_sddma_stb_sent <= '0';
+                elsif wb_sddma_in.stall = '0' then
+                    wb_sddma_stb_sent <= wb_sddma_nr.stb;
+                end if;
+                wb_sddma_ir <= wb_sddma_in;
+            end if;
+        end process;
+
+    end generate;
+
+    -- Mux WB response on the IO bus
+    wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
+                     wb_sdcard_out when wb_ext_is_sdcard = '1' else
+                     wb_dram_ctrl_out;
+
+    led0_n <= system_clk_locked;
+    led1_n <= not soc_rst;
+
+end architecture behaviour;

fpga/wukong-v2.xdc

@@ -0,0 +1,487 @@
+################################################################################
+# clkin, reset, uart pins...
+################################################################################
+
+set_property -dict { PACKAGE_PIN M21  IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
+
+set_property -dict { PACKAGE_PIN H7   IOSTANDARD LVCMOS33 } [get_ports { ext_rst_n }];
+
+set_property -dict { PACKAGE_PIN E3   IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
+set_property -dict { PACKAGE_PIN F3   IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
+
+################################################################################
+# LEDs
+################################################################################
+
+set_property -dict { PACKAGE_PIN V16  IOSTANDARD LVCMOS33 } [get_ports { led0_n }];
+set_property -dict { PACKAGE_PIN V17  IOSTANDARD LVCMOS33 } [get_ports { led1_n }];
+
+################################################################################
+# SPI Flash
+################################################################################ema
+
+set_property -dict { PACKAGE_PIN P18  IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }];
+set_property -dict { PACKAGE_PIN R14  IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }];
+set_property -dict { PACKAGE_PIN R15  IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }];
+set_property -dict { PACKAGE_PIN P14  IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
+set_property -dict { PACKAGE_PIN N14  IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
+
+################################################################################
+# Micro SD
+################################################################################
+
+set_property -dict { PACKAGE_PIN M5   IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[0] }];
+set_property -dict { PACKAGE_PIN M7   IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[1] }];
+set_property -dict { PACKAGE_PIN H6   IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[2] }];
+set_property -dict { PACKAGE_PIN J6   IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[3] }];
+set_property -dict { PACKAGE_PIN J8   IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_cmd }];
+set_property -dict { PACKAGE_PIN L4   IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }];
+set_property -dict { PACKAGE_PIN N6   IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }];
+
+# Put registers into IOBs to improve timing
+set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdcard_*}]
+
+################################################################################
+# PMOD header J10 (high-speed, no protection resisters)
+################################################################################
+
+#set_property -dict { PACKAGE_PIN D5   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_1 }];
+#set_property -dict { PACKAGE_PIN G5   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_2 }];
+#set_property -dict { PACKAGE_PIN G7   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_3 }];
+#set_property -dict { PACKAGE_PIN G8   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_4 }];
+#set_property -dict { PACKAGE_PIN E5   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_7 }];
+#set_property -dict { PACKAGE_PIN E6   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_8 }];
+#set_property -dict { PACKAGE_PIN D6   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_9 }];
+#set_property -dict { PACKAGE_PIN G6   IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_10 }];
+
+################################################################################
+# PMOD header J11 (high-speed, no protection resisters)
+################################################################################
+
+#set_property -dict { PACKAGE_PIN H4   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_1 }];
+#set_property -dict { PACKAGE_PIN F4   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_2 }];
+#set_property -dict { PACKAGE_PIN A4   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_3 }];
+#set_property -dict { PACKAGE_PIN A5   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_4 }];
+#set_property -dict { PACKAGE_PIN J4   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_7 }];
+#set_property -dict { PACKAGE_PIN G4   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_8 }];
+#set_property -dict { PACKAGE_PIN B4   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_9 }];
+#set_property -dict { PACKAGE_PIN B5   IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_10 }];
+
+################################################################################
+# HDR 20X2 connector
+################################################################################
+
+## TODO
+
+################################################################################
+# Ethernet (generated by LiteX)
+################################################################################
+
+# eth_clocks:0.tx
+set_property LOC M2 [get_ports {eth_clocks_tx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}]
+
+# eth_clocks:0.gtx
+set_property LOC U1 [get_ports {eth_clocks_gtx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_gtx}]
+
+# eth_clocks:0.rx
+set_property LOC P4 [get_ports {eth_clocks_rx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}]
+
+# eth:0.rst_n
+set_property LOC R1 [get_ports {eth_rst_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}]
+
+# eth:0.mdio
+set_property LOC H1 [get_ports {eth_mdio}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}]
+
+# eth:0.mdc
+set_property LOC H2 [get_ports {eth_mdc}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}]
+
+# eth:0.rx_dv
+set_property LOC L3 [get_ports {eth_rx_dv}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_dv}]
+
+# eth:0.rx_er
+set_property LOC U5 [get_ports {eth_rx_er}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}]
+
+# eth:0.rx_data
+set_property LOC M4 [get_ports {eth_rx_data[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]
+
+# eth:0.rx_data
+set_property LOC N3 [get_ports {eth_rx_data[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]
+
+# eth:0.rx_data
+set_property LOC N4 [get_ports {eth_rx_data[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]
+
+# eth:0.rx_data
+set_property LOC P3 [get_ports {eth_rx_data[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]
+
+# eth:0.rx_data
+set_property LOC R3 [get_ports {eth_rx_data[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[4]}]
+
+# eth:0.rx_data
+set_property LOC T3 [get_ports {eth_rx_data[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[5]}]
+
+# eth:0.rx_data
+set_property LOC T4 [get_ports {eth_rx_data[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[6]}]
+
+# eth:0.rx_data
+set_property LOC T5 [get_ports {eth_rx_data[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[7]}]
+
+# eth:0.tx_en
+set_property LOC T2 [get_ports {eth_tx_en}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}]
+
+# eth:0.tx_er
+set_property LOC J1 [get_ports {eth_tx_er}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_er}]
+
+# eth:0.tx_data
+set_property LOC R2 [get_ports {eth_tx_data[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]
+
+# eth:0.tx_data
+set_property LOC P1 [get_ports {eth_tx_data[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]
+
+# eth:0.tx_data
+set_property LOC N2 [get_ports {eth_tx_data[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]
+
+# eth:0.tx_data
+set_property LOC N1 [get_ports {eth_tx_data[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]
+
+# eth:0.tx_data
+set_property LOC M1 [get_ports {eth_tx_data[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[4]}]
+
+# eth:0.tx_data
+set_property LOC L2 [get_ports {eth_tx_data[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[5]}]
+
+# eth:0.tx_data
+set_property LOC K2 [get_ports {eth_tx_data[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[6]}]
+
+# eth:0.tx_data
+set_property LOC K1 [get_ports {eth_tx_data[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[7]}]
+
+# eth:0.col
+set_property LOC U4 [get_ports {eth_col}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_col}]
+
+# eth:0.crs
+set_property LOC U2 [get_ports {eth_crs}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs}]
+
+################################################################################
+# DRAM (generated by LiteX)
+################################################################################
+
+# ddram:0.a
+set_property LOC E17 [get_ports {ddram_a[0]}]
+set_property SLEW FAST [get_ports {ddram_a[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}]
+
+# ddram:0.a
+set_property LOC G17 [get_ports {ddram_a[1]}]
+set_property SLEW FAST [get_ports {ddram_a[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}]
+
+# ddram:0.a
+set_property LOC F17 [get_ports {ddram_a[2]}]
+set_property SLEW FAST [get_ports {ddram_a[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}]
+
+# ddram:0.a
+set_property LOC C17 [get_ports {ddram_a[3]}]
+set_property SLEW FAST [get_ports {ddram_a[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}]
+
+# ddram:0.a
+set_property LOC G16 [get_ports {ddram_a[4]}]
+set_property SLEW FAST [get_ports {ddram_a[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}]
+
+# ddram:0.a
+set_property LOC D16 [get_ports {ddram_a[5]}]
+set_property SLEW FAST [get_ports {ddram_a[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}]
+
+# ddram:0.a
+set_property LOC H16 [get_ports {ddram_a[6]}]
+set_property SLEW FAST [get_ports {ddram_a[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}]
+
+# ddram:0.a
+set_property LOC E16 [get_ports {ddram_a[7]}]
+set_property SLEW FAST [get_ports {ddram_a[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}]
+
+# ddram:0.a
+set_property LOC H14 [get_ports {ddram_a[8]}]
+set_property SLEW FAST [get_ports {ddram_a[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}]
+
+# ddram:0.a
+set_property LOC F15 [get_ports {ddram_a[9]}]
+set_property SLEW FAST [get_ports {ddram_a[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}]
+
+# ddram:0.a
+set_property LOC F20 [get_ports {ddram_a[10]}]
+set_property SLEW FAST [get_ports {ddram_a[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}]
+
+# ddram:0.a
+set_property LOC H15 [get_ports {ddram_a[11]}]
+set_property SLEW FAST [get_ports {ddram_a[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}]
+
+# ddram:0.a
+set_property LOC C18 [get_ports {ddram_a[12]}]
+set_property SLEW FAST [get_ports {ddram_a[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}]
+
+# ddram:0.a
+set_property LOC G15 [get_ports {ddram_a[13]}]
+set_property SLEW FAST [get_ports {ddram_a[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}]
+
+# ddram:0.ba
+set_property LOC B17 [get_ports {ddram_ba[0]}]
+set_property SLEW FAST [get_ports {ddram_ba[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}]
+
+# ddram:0.ba
+set_property LOC D18 [get_ports {ddram_ba[1]}]
+set_property SLEW FAST [get_ports {ddram_ba[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}]
+
+# ddram:0.ba
+set_property LOC A17 [get_ports {ddram_ba[2]}]
+set_property SLEW FAST [get_ports {ddram_ba[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}]
+
+# ddram:0.ras_n
+set_property LOC A19 [get_ports {ddram_ras_n}]
+set_property SLEW FAST [get_ports {ddram_ras_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}]
+
+# ddram:0.cas_n
+set_property LOC B19 [get_ports {ddram_cas_n}]
+set_property SLEW FAST [get_ports {ddram_cas_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}]
+
+# ddram:0.we_n
+set_property LOC A18 [get_ports {ddram_we_n}]
+set_property SLEW FAST [get_ports {ddram_we_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}]
+
+# ddram:0.dm
+set_property LOC A22 [get_ports {ddram_dm[0]}]
+set_property SLEW FAST [get_ports {ddram_dm[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}]
+
+# ddram:0.dm
+set_property LOC C22 [get_ports {ddram_dm[1]}]
+set_property SLEW FAST [get_ports {ddram_dm[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}]
+
+# ddram:0.dq
+set_property LOC D21 [get_ports {ddram_dq[0]}]
+set_property SLEW FAST [get_ports {ddram_dq[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}]
+
+# ddram:0.dq
+set_property LOC C21 [get_ports {ddram_dq[1]}]
+set_property SLEW FAST [get_ports {ddram_dq[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}]
+
+# ddram:0.dq
+set_property LOC B22 [get_ports {ddram_dq[2]}]
+set_property SLEW FAST [get_ports {ddram_dq[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}]
+
+# ddram:0.dq
+set_property LOC B21 [get_ports {ddram_dq[3]}]
+set_property SLEW FAST [get_ports {ddram_dq[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}]
+
+# ddram:0.dq
+set_property LOC D19 [get_ports {ddram_dq[4]}]
+set_property SLEW FAST [get_ports {ddram_dq[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}]
+
+# ddram:0.dq
+set_property LOC E20 [get_ports {ddram_dq[5]}]
+set_property SLEW FAST [get_ports {ddram_dq[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}]
+
+# ddram:0.dq
+set_property LOC C19 [get_ports {ddram_dq[6]}]
+set_property SLEW FAST [get_ports {ddram_dq[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}]
+
+# ddram:0.dq
+set_property LOC D20 [get_ports {ddram_dq[7]}]
+set_property SLEW FAST [get_ports {ddram_dq[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}]
+
+# ddram:0.dq
+set_property LOC C23 [get_ports {ddram_dq[8]}]
+set_property SLEW FAST [get_ports {ddram_dq[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}]
+
+# ddram:0.dq
+set_property LOC D23 [get_ports {ddram_dq[9]}]
+set_property SLEW FAST [get_ports {ddram_dq[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}]
+
+# ddram:0.dq
+set_property LOC B24 [get_ports {ddram_dq[10]}]
+set_property SLEW FAST [get_ports {ddram_dq[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}]
+
+# ddram:0.dq
+set_property LOC B25 [get_ports {ddram_dq[11]}]
+set_property SLEW FAST [get_ports {ddram_dq[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}]
+
+# ddram:0.dq
+set_property LOC C24 [get_ports {ddram_dq[12]}]
+set_property SLEW FAST [get_ports {ddram_dq[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}]
+
+# ddram:0.dq
+set_property LOC C26 [get_ports {ddram_dq[13]}]
+set_property SLEW FAST [get_ports {ddram_dq[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}]
+
+# ddram:0.dq
+set_property LOC A25 [get_ports {ddram_dq[14]}]
+set_property SLEW FAST [get_ports {ddram_dq[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}]
+
+# ddram:0.dq
+set_property LOC B26 [get_ports {ddram_dq[15]}]
+set_property SLEW FAST [get_ports {ddram_dq[15]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}]
+
+# ddram:0.dqs_p
+set_property LOC B20 [get_ports {ddram_dqs_p[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}]
+
+# ddram:0.dqs_p
+set_property LOC A23 [get_ports {ddram_dqs_p[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}]
+
+# ddram:0.dqs_n
+set_property LOC A20 [get_ports {ddram_dqs_n[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}]
+
+# ddram:0.dqs_n
+set_property LOC A24 [get_ports {ddram_dqs_n[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}]
+
+# ddram:0.clk_p
+set_property LOC F18 [get_ports {ddram_clk_p}]
+set_property SLEW FAST [get_ports {ddram_clk_p}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}]
+
+# ddram:0.clk_n
+set_property LOC F19 [get_ports {ddram_clk_n}]
+set_property SLEW FAST [get_ports {ddram_clk_n}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}]
+
+# ddram:0.cke
+set_property LOC E18 [get_ports {ddram_cke}]
+set_property SLEW FAST [get_ports {ddram_cke}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}]
+
+# ddram:0.odt
+set_property LOC G19 [get_ports {ddram_odt}]
+set_property SLEW FAST [get_ports {ddram_odt}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}]
+
+# ddram:0.reset_n
+set_property LOC H17 [get_ports {ddram_reset_n}]
+set_property SLEW FAST [get_ports {ddram_reset_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}]
+
+################################################################################
+# Design constraints and bitsteam attributes
+################################################################################
+
+set_property INTERNAL_VREF 0.675 [get_iobanks 16]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+################################################################################
+# Clock constraints
+################################################################################
+
+create_clock -name sys_clk_pin -period 20.00 [get_ports { ext_clk }];
+
+create_clock -name eth_rx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_rx_clk]
+create_clock -name eth_tx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_tx_clk]
+
+set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -asynchronous
+
+set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous
+
+set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous
+
+################################################################################
+# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth)
+################################################################################
+
+set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
+
+set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
+
+set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]

litedram/gen-src/generate.py

@@ -100,7 +100,7 @@ def generate_one(t):
 
 def main():
 
-    targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'sim']
+    targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'sim']
     for t in targets:
         generate_one(t)
     

litedram/gen-src/sdram_init/main.c

@@ -125,7 +125,7 @@ static bool check_flash(void)
 
 	/* Supported flash types for quad mode */
 	if (id[0] == 0x01 &&
-	    (id[1] == 0x02 || id[1] == 0x20) &&
+	    (id[1] == 0x02 || id[1] == 0x20 || id[1] == 0x60) &&
 	    (id[2] == 0x18 || id[2] == 0x19)) {
 		check_spansion_quad_mode();
 		quad = true;

litedram/gen-src/wukong-v2.yml

@@ -0,0 +1,36 @@
+# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+{
+    # General ------------------------------------------------------------------
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
+    "speedgrade": -1,          # FPGA speedgrade
+    "memtype":    "DDR3",      # DRAM type
+
+    # PHY ----------------------------------------------------------------------
+    "cmd_latency":     0,             # Command additional latency
+    "sdram_module":    "MT41K128M16", # SDRAM modules of the board or SO-DIMM
+    "sdram_module_nb": 2,             # Number of byte groups
+    "sdram_rank_nb":   1,             # Number of ranks
+    "sdram_phy":       "A7DDRPHY",    # Type of FPGA PHY
+
+    # Electrical ---------------------------------------------------------------
+    "rtt_nom": "60ohm",  # Nominal termination
+    "rtt_wr":  "60ohm",  # Write termination
+    "ron":     "34ohm",  # Output driver impedance
+
+    # Frequency ----------------------------------------------------------------
+    "input_clk_freq":   50e6, # Input clock frequency
+    "sys_clk_freq":     100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+    "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
+
+    # Core ---------------------------------------------------------------------
+    "cmd_buffer_depth": 16,    # Depth of the command buffer
+
+    # User Ports ---------------------------------------------------------------
+    "user_ports": {
+        "native_0": {
+            "type": "native",
+        },
+    },
+}

litedram/generated/nexys-video/litedram_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:12
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:33
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
@@ -4587,10 +4587,10 @@ end
 reg dummy_d_103;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
+	main_litedramcore_slave_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
 // synthesis translate_off
 	dummy_d_103 = dummy_s;
@@ -4616,10 +4616,10 @@ end
 reg dummy_d_105;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	main_litedramcore_inti_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
 // synthesis translate_off
 	dummy_d_105 = dummy_s;
@@ -4645,11 +4645,10 @@ end
 reg dummy_d_107;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_rddata_en <= 1'd0;
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
 	end else begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
 // synthesis translate_off
 	dummy_d_107 = dummy_s;
@@ -4660,11 +4659,11 @@ end
 reg dummy_d_108;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p3_address <= 15'd0;
+	main_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
 	end else begin
-		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
 // synthesis translate_off
 	dummy_d_108 = dummy_s;
@@ -4675,10 +4674,11 @@ end
 reg dummy_d_109;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 32'd0;
+	main_litedramcore_master_p3_address <= 15'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
 	end else begin
+		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
 // synthesis translate_off
 	dummy_d_109 = dummy_s;
@@ -11032,10 +11032,14 @@ end
 reg dummy_d_288;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
+	main_litedramcore_choose_req_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -11056,6 +11060,11 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11066,6 +11075,41 @@ end
 // synthesis translate_off
 reg dummy_d_289;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_en1 <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_en1 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_289 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_290;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11108,12 +11152,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_289 = dummy_s;
+	dummy_d_290 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_290;
+reg dummy_d_291;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel1 <= 2'd0;
@@ -11156,12 +11200,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_290 = dummy_s;
+	dummy_d_291 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_291;
+reg dummy_d_292;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_ready <= 1'd0;
@@ -11191,12 +11235,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_291 = dummy_s;
+	dummy_d_292 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_292;
+reg dummy_d_293;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
@@ -11239,12 +11283,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_292 = dummy_s;
+	dummy_d_293 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_293;
+reg dummy_d_294;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_want_activates <= 1'd0;
@@ -11281,12 +11325,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_293 = dummy_s;
+	dummy_d_294 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_294;
+reg dummy_d_295;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel3 <= 2'd0;
@@ -11329,12 +11373,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_294 = dummy_s;
+	dummy_d_295 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_296;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_en0 <= 1'd0;
@@ -11364,12 +11408,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_295 = dummy_s;
+	dummy_d_296 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
@@ -11405,41 +11449,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_296 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_297 = dummy_s;
 // synthesis translate_on
@@ -11449,10 +11458,9 @@ end
 reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
+	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11473,6 +11481,7 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 // synthesis translate_off
@@ -11484,14 +11493,10 @@ end
 reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
+			main_litedramcore_choose_req_want_writes <= 1'd1;
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -11512,11 +11517,6 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -11571,13 +11571,13 @@ assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
 reg dummy_d_300;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 16'd0;
+	main_litedramcore_interface_wdata <= 128'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 // synthesis translate_off
@@ -11589,13 +11589,13 @@ end
 reg dummy_d_301;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata <= 128'd0;
+	main_litedramcore_interface_wdata_we <= 16'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 // synthesis translate_off
@@ -11810,7 +11810,7 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -11867,7 +11867,7 @@ always @(*) begin
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -11928,9 +11928,9 @@ assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_319;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_319 = dummy_s;
@@ -11941,9 +11941,9 @@ end
 reg dummy_d_320;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_320 = dummy_s;
@@ -11955,9 +11955,9 @@ assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_321;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_321 = dummy_s;
@@ -11968,9 +11968,9 @@ end
 reg dummy_d_322;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_322 = dummy_s;
@@ -12063,9 +12063,9 @@ assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0
 reg dummy_d_329;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_329 = dummy_s;
@@ -12076,9 +12076,9 @@ end
 reg dummy_d_330;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_330 = dummy_s;
@@ -12225,7 +12225,7 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 
 // synthesis translate_off
@@ -12313,9 +12313,9 @@ assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_347;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_347 = dummy_s;
@@ -12326,9 +12326,9 @@ end
 reg dummy_d_348;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_348 = dummy_s;
@@ -12421,9 +12421,9 @@ assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_355;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_355 = dummy_s;
@@ -12434,9 +12434,9 @@ end
 reg dummy_d_356;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_356 = dummy_s;
@@ -12664,9 +12664,9 @@ assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_373;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_373 = dummy_s;
@@ -12677,9 +12677,9 @@ end
 reg dummy_d_374;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_374 = dummy_s;
@@ -12772,9 +12772,9 @@ assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_381;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_381 = dummy_s;
@@ -12785,9 +12785,9 @@ end
 reg dummy_d_382;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_382 = dummy_s;
@@ -12988,9 +12988,9 @@ assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_ban
 reg dummy_d_397;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_397 = dummy_s;
@@ -13001,9 +13001,9 @@ end
 reg dummy_d_398;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_398 = dummy_s;
@@ -13015,9 +13015,9 @@ assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_399;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_399 = dummy_s;
@@ -13028,9 +13028,9 @@ end
 reg dummy_d_400;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_400 = dummy_s;
@@ -13123,9 +13123,9 @@ assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_407;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_407 = dummy_s;
@@ -13136,9 +13136,9 @@ end
 reg dummy_d_408;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_408 = dummy_s;
@@ -13366,9 +13366,9 @@ assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_425;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_425 = dummy_s;
@@ -13379,9 +13379,9 @@ end
 reg dummy_d_426;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_426 = dummy_s;
@@ -13474,9 +13474,9 @@ assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_433;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_433 = dummy_s;
@@ -13487,9 +13487,9 @@ end
 reg dummy_d_434;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_434 = dummy_s;

litedram/generated/sim/litedram_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:19
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:42
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire sim_trace,
@@ -2124,36 +2124,36 @@ always @(*) begin
 	soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_activate = 1'd0;
+	soc_ddrphy_bankmodel1_activate_row = 14'd0;
 	case (soc_ddrphy_activates1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_activate_row = 14'd0;
+	soc_ddrphy_bankmodel1_activate = 1'd0;
 	case (soc_ddrphy_activates1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
 		end
 	endcase
 end
@@ -2838,36 +2838,36 @@ always @(*) begin
 	soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_read_col = 10'd0;
+	soc_ddrphy_bankmodel5_read = 1'd0;
 	case (soc_ddrphy_reads5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_read = 1'd0;
+	soc_ddrphy_bankmodel5_read_col = 10'd0;
 	case (soc_ddrphy_reads5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -3030,36 +3030,36 @@ always @(*) begin
 	soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_activate_row = 14'd0;
+	soc_ddrphy_bankmodel7_activate = 1'd0;
 	case (soc_ddrphy_activates7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_activate = 1'd0;
+	soc_ddrphy_bankmodel7_activate_row = 14'd0;
 	case (soc_ddrphy_activates7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -3140,36 +3140,36 @@ always @(*) begin
 	soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_read = 1'd0;
+	soc_ddrphy_bankmodel7_read_col = 10'd0;
 	case (soc_ddrphy_reads7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_read_col = 10'd0;
+	soc_ddrphy_bankmodel7_read = 1'd0;
 	case (soc_ddrphy_reads7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
 		end
 	endcase
 end
@@ -3321,6 +3321,14 @@ always @(*) begin
 end
 assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
 assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
+always @(*) begin
+	soc_ddrphy_bankmodel1_read_data = 128'd0;
+	if (soc_ddrphy_bankmodel1_active) begin
+		if (soc_ddrphy_bankmodel1_read) begin
+			soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
+		end
+	end
+end
 always @(*) begin
 	soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
 	if (soc_ddrphy_bankmodel1_active) begin
@@ -3351,14 +3359,6 @@ always @(*) begin
 		end
 	end
 end
-always @(*) begin
-	soc_ddrphy_bankmodel1_read_data = 128'd0;
-	if (soc_ddrphy_bankmodel1_active) begin
-		if (soc_ddrphy_bankmodel1_read) begin
-			soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
-		end
-	end
-end
 assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
 assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
 always @(*) begin
@@ -3441,6 +3441,12 @@ always @(*) begin
 end
 assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
 assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
+always @(*) begin
+	soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
+	if (soc_ddrphy_bankmodel4_active) begin
+		soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
+	end
+end
 always @(*) begin
 	soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
 	if (soc_ddrphy_bankmodel4_active) begin
@@ -3473,12 +3479,6 @@ always @(*) begin
 		end
 	end
 end
-always @(*) begin
-	soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
-	if (soc_ddrphy_bankmodel4_active) begin
-		soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
-	end
-end
 assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
 assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
 always @(*) begin
@@ -3944,14 +3944,6 @@ always @(*) begin
 		soc_litedramcore_inti_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid;
 	end
 end
-always @(*) begin
-	soc_litedramcore_master_p0_ras_n = 1'd1;
-	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
-	end else begin
-		soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
-	end
-end
 always @(*) begin
 	soc_litedramcore_master_p1_wrdata_mask = 4'd0;
 	if (soc_litedramcore_sel) begin
@@ -3968,6 +3960,14 @@ always @(*) begin
 		soc_litedramcore_master_p1_rddata_en = soc_litedramcore_inti_p1_rddata_en;
 	end
 end
+always @(*) begin
+	soc_litedramcore_master_p0_ras_n = 1'd1;
+	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
+	end else begin
+		soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
+	end
+end
 always @(*) begin
 	soc_litedramcore_master_p2_address = 14'd0;
 	if (soc_litedramcore_sel) begin
@@ -9670,10 +9670,10 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_en1 = 1'd0;
+	soc_litedramcore_choose_req_want_writes = 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_en1 = 1'd1;
+			soc_litedramcore_choose_req_want_writes = 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9698,10 +9698,10 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_choose_req_want_writes = 1'd0;
+	soc_litedramcore_en1 = 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_choose_req_want_writes = 1'd1;
+			soc_litedramcore_en1 = 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9806,24 +9806,24 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) &
 assign soc_user_port_wdata_ready = new_master_wdata_ready1;
 assign soc_user_port_rdata_valid = new_master_rdata_valid8;
 always @(*) begin
-	soc_litedramcore_interface_wdata_we = 16'd0;
+	soc_litedramcore_interface_wdata = 128'd0;
 	case ({new_master_wdata_ready1})
 		1'd1: begin
-			soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
+			soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
 		end
 		default: begin
-			soc_litedramcore_interface_wdata_we = 1'd0;
+			soc_litedramcore_interface_wdata = 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_interface_wdata = 128'd0;
+	soc_litedramcore_interface_wdata_we = 16'd0;
 	case ({new_master_wdata_ready1})
 		1'd1: begin
-			soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
+			soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
 		end
 		default: begin
-			soc_litedramcore_interface_wdata = 1'd0;
+			soc_litedramcore_interface_wdata_we = 1'd0;
 		end
 	endcase
 end
@@ -9853,6 +9853,21 @@ always @(*) begin
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_adr_next_value1 = 14'd0;
+	case (state)
+		1'd1: begin
+			litedramcore_adr_next_value1 = 1'd0;
+		end
+		2'd2: begin
+		end
+		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
+			end
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_adr_next_value_ce1 = 1'd0;
 	case (state)
@@ -9946,21 +9961,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_adr_next_value1 = 14'd0;
-	case (state)
-		1'd1: begin
-			litedramcore_adr_next_value1 = 1'd0;
-		end
-		2'd2: begin
-		end
-		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
-			end
-		end
-	endcase
-end
 assign litedramcore_wishbone_adr = soc_wb_bus_adr;
 assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
 assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r;
@@ -9972,7 +9972,7 @@ assign litedramcore_wishbone_we = soc_wb_bus_we;
 assign litedramcore_wishbone_cti = soc_wb_bus_cti;
 assign litedramcore_wishbone_bte = soc_wb_bus_bte;
 assign soc_wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd1);
 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
 	csrbank0_init_done0_we = 1'd0;
@@ -10001,7 +10001,7 @@ always @(*) begin
 end
 assign csrbank0_init_done0_w = soc_init_done_storage;
 assign csrbank0_init_error0_w = soc_init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
 assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
 always @(*) begin
 	csrbank1_dfii_control0_re = 1'd0;
@@ -10017,15 +10017,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi0_command0_re = 1'd0;
+	csrbank1_dfii_pi0_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_command0_we = 1'd0;
+	csrbank1_dfii_pi0_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
@@ -10082,15 +10082,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi0_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi0_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi0_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10134,15 +10134,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi0_rddata3_re = 1'd0;
+	csrbank1_dfii_pi0_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_rddata3_we = 1'd0;
+	csrbank1_dfii_pi0_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10160,15 +10160,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi0_rddata1_we = 1'd0;
+	csrbank1_dfii_pi0_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_rddata1_re = 1'd0;
+	csrbank1_dfii_pi0_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
@@ -10186,15 +10186,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi1_command0_re = 1'd0;
+	csrbank1_dfii_pi1_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_command0_we = 1'd0;
+	csrbank1_dfii_pi1_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
@@ -10251,15 +10251,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi1_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi1_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
-		csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi1_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
-		csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10303,15 +10303,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi1_rddata3_re = 1'd0;
+	csrbank1_dfii_pi1_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-		csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_rddata3_we = 1'd0;
+	csrbank1_dfii_pi1_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-		csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10329,15 +10329,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi1_rddata1_we = 1'd0;
+	csrbank1_dfii_pi1_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
-		csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_rddata1_re = 1'd0;
+	csrbank1_dfii_pi1_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
-		csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
@@ -10355,28 +10355,28 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi2_command0_re = 1'd0;
+	csrbank1_dfii_pi2_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
-		csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_command0_we = 1'd0;
+	csrbank1_dfii_pi2_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
-		csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+	soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
-		soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
+		soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+	soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
-		soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
+		soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
@@ -10420,15 +10420,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi2_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
-		csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi2_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
-		csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10472,15 +10472,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata3_re = 1'd0;
+	csrbank1_dfii_pi2_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
-		csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata3_we = 1'd0;
+	csrbank1_dfii_pi2_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
-		csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10498,15 +10498,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata1_we = 1'd0;
+	csrbank1_dfii_pi2_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
-		csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata1_re = 1'd0;
+	csrbank1_dfii_pi2_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
-		csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
@@ -10524,15 +10524,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi3_command0_re = 1'd0;
+	csrbank1_dfii_pi3_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
-		csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_command0_we = 1'd0;
+	csrbank1_dfii_pi3_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
-		csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
@@ -10589,15 +10589,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi3_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
-		csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi3_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
-		csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10641,15 +10641,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata3_re = 1'd0;
+	csrbank1_dfii_pi3_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
-		csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata3_we = 1'd0;
+	csrbank1_dfii_pi3_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
-		csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10667,15 +10667,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata1_we = 1'd0;
+	csrbank1_dfii_pi3_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
-		csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata1_re = 1'd0;
+	csrbank1_dfii_pi3_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
-		csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];

litedram/generated/wukong-v2/litedram-initmem.vhdl

@@ -0,0 +1,123 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.utils.all;
+
+entity dram_init_mem is
+    generic (
+        EXTRA_PAYLOAD_FILE : string   := "";
+        EXTRA_PAYLOAD_SIZE : integer  := 0
+        );
+    port (
+        clk     : in std_ulogic;
+        wb_in   : in wb_io_master_out;
+        wb_out  : out wb_io_slave_out
+      );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+    constant INIT_RAM_SIZE    : integer := 24576;
+    constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
+    constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
+    constant INIT_RAM_FILE    : string := "litedram_core.init";
+
+    type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+    -- XXX FIXME: Have a single init function called twice with
+    -- an offset as argument
+    procedure init_load_payload(ram: inout ram_t; filename: string) is
+        file payload_file : text open read_mode is filename;
+        variable ram_line : line;
+        variable temp_word : std_logic_vector(63 downto 0);
+    begin
+        for i in 0 to RND_PAYLOAD_SIZE-1 loop
+            exit when endfile(payload_file);
+            readline(payload_file, ram_line);
+            hread(ram_line, temp_word);
+            ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
+            ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
+        end loop;
+        assert endfile(payload_file) report "Payload too big !" severity failure;
+    end procedure;
+
+    impure function init_load_ram(name : string) return ram_t is
+        file ram_file : text open read_mode is name;
+        variable temp_word : std_logic_vector(63 downto 0);
+        variable temp_ram : ram_t := (others => (others => '0'));
+        variable ram_line : line;
+    begin
+        report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
+            " rounded to:" & integer'image(RND_PAYLOAD_SIZE);
+        report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
+            " bytes using " & integer'image(INIT_RAM_ABITS) &
+            " address bits";
+        for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+            exit when endfile(ram_file);
+            readline(ram_file, ram_line);
+            hread(ram_line, temp_word);
+            temp_ram(i*2) := temp_word(31 downto 0);
+            temp_ram(i*2+1) := temp_word(63 downto 32);
+        end loop;
+        if RND_PAYLOAD_SIZE /= 0 then
+            init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
+        end if;
+        return temp_ram;
+    end function;
+
+    impure function init_zero return ram_t is
+        variable temp_ram : ram_t := (others => (others => '0'));
+    begin
+        return temp_ram;
+    end function;
+
+    impure function initialize_ram(filename: string) return ram_t is
+    begin
+        report "Opening file " & filename;
+        if filename'length = 0 then
+            return init_zero;
+        else
+            return init_load_ram(filename);
+        end if;
+    end function;
+    signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
+    signal obuf : std_ulogic_vector(31 downto 0);
+    signal oack : std_ulogic;
+begin
+
+    init_ram_0: process(clk)
+        variable adr  : integer;
+    begin
+        if rising_edge(clk) then
+            oack <= '0';
+            if (wb_in.cyc and wb_in.stb) = '1' then
+                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+                if wb_in.we = '0' then
+                   obuf <= init_ram(adr);
+                else
+                    for i in 0 to 3 loop
+                        if wb_in.sel(i) = '1' then
+                            init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+                                wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+                        end if;
+                    end loop;
+                end if;
+                oack <= '1';
+            end if;
+            wb_out.ack <= oack;
+            wb_out.dat <= obuf;
+        end if;
+    end process;
+
+    wb_out.stall <= '0';
+
+end architecture rtl;

liteeth/gen-src/generate.sh

@@ -1,6 +1,6 @@
 #!/bin/bash
 
-TARGETS="arty nexys-video"
+TARGETS="arty nexys-video wukong-v2"
 
 ME=$(realpath $0)
 echo ME=$ME

liteeth/gen-src/wukong-v2.yml

@@ -0,0 +1,17 @@
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+# PHY ----------------------------------------------------------------------
+phy:        LiteEthPHYGMIIMII
+vendor:     xilinx
+device:     xc7
+# Core ---------------------------------------------------------------------
+clk_freq:   100e6
+core:       wishbone
+endianness: little
+ntxslots:   2
+nrxslots:   2
+
+soc:
+    mem_map:
+        ethmac: 0x00010000

liteeth/generated/arty/liteeth_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (--------) on 2021-08-09 13:54:48
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:00
 //--------------------------------------------------------------------------------
 module liteeth_core(
 	input wire sys_clock,
@@ -41,15 +41,15 @@ wire main_maccore_maccore_bus_errors_we;
 reg main_maccore_maccore_bus_errors_re = 1'd0;
 wire main_maccore_maccore_bus_error;
 reg [31:0] main_maccore_maccore_bus_errors = 32'd0;
-wire sys_clk;
+(* dont_touch = "true" *) wire sys_clk;
 wire sys_rst;
 wire por_clk;
 reg main_maccore_int_rst = 1'd1;
 reg main_maccore_ethphy_reset_storage = 1'd0;
 reg main_maccore_ethphy_reset_re = 1'd0;
-wire eth_rx_clk;
+(* dont_touch = "true" *) wire eth_rx_clk;
 wire eth_rx_rst;
-wire eth_tx_clk;
+(* dont_touch = "true" *) wire eth_tx_clk;
 wire eth_tx_rst;
 wire main_maccore_ethphy_reset0;
 wire main_maccore_ethphy_reset1;
@@ -1260,13 +1260,13 @@ end
 assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data;
 assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be;
 always @(*) begin
+	builder_liteethmacpreamblechecker_next_state <= 1'd0;
 	main_preamble_checker_source_first <= 1'd0;
 	main_preamble_checker_sink_ready <= 1'd0;
 	main_preamble_checker_source_last <= 1'd0;
 	main_preamble_checker_source_payload_error <= 1'd0;
 	main_preamble_checker_error <= 1'd0;
 	main_preamble_checker_source_valid <= 1'd0;
-	builder_liteethmacpreamblechecker_next_state <= 1'd0;
 	builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state;
 	case (builder_liteethmacpreamblechecker_state)
 		1'd1: begin
@@ -1602,13 +1602,13 @@ assign main_padding_checker_source_payload_data = main_padding_checker_sink_payl
 assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be;
 assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error;
 always @(*) begin
+	main_tx_last_be_source_valid <= 1'd0;
 	main_tx_last_be_sink_ready <= 1'd0;
 	main_tx_last_be_source_first <= 1'd0;
 	main_tx_last_be_source_last <= 1'd0;
 	main_tx_last_be_source_payload_data <= 8'd0;
 	main_tx_last_be_source_payload_error <= 1'd0;
 	builder_liteethmactxlastbe_next_state <= 1'd0;
-	main_tx_last_be_source_valid <= 1'd0;
 	builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state;
 	case (builder_liteethmactxlastbe_state)
 		1'd1: begin
@@ -2041,15 +2041,15 @@ assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r;
 assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2);
 assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0);
 always @(*) begin
+	main_writer_start <= 1'd0;
+	main_writer_counter_t_next_value_ce <= 1'd0;
 	main_writer_ongoing <= 1'd0;
+	main_writer_slot_ce <= 1'd0;
 	main_writer_errors_status_f_next_value <= 32'd0;
 	main_writer_stat_fifo_sink_valid <= 1'd0;
 	main_writer_errors_status_f_next_value_ce <= 1'd0;
-	main_writer_start <= 1'd0;
 	builder_liteethmacsramwriter_next_state <= 3'd0;
 	main_writer_counter_t_next_value <= 32'd0;
-	main_writer_slot_ce <= 1'd0;
-	main_writer_counter_t_next_value_ce <= 1'd0;
 	builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state;
 	case (builder_liteethmacsramwriter_state)
 		1'd1: begin
@@ -2181,6 +2181,7 @@ assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r;
 assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2);
 assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0);
 always @(*) begin
+	main_reader_source_source_last <= 1'd0;
 	builder_liteethmacsramreader_next_state <= 2'd0;
 	main_reader_counter_next_value <= 11'd0;
 	main_reader_read_address <= 11'd0;
@@ -2189,7 +2190,6 @@ always @(*) begin
 	main_reader_eventsourcepulse_trigger <= 1'd0;
 	main_reader_source_source_valid <= 1'd0;
 	main_reader_start <= 1'd0;
-	main_reader_source_source_last <= 1'd0;
 	builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state;
 	case (builder_liteethmacsramreader_state)
 		1'd1: begin
@@ -2292,8 +2292,8 @@ always @(*) begin
 	builder_maccore_wishbone_dat_r <= 32'd0;
 	builder_maccore_adr <= 14'd0;
 	builder_maccore_we <= 1'd0;
-	builder_maccore_dat_w <= 32'd0;
 	builder_maccore_wishbone_ack <= 1'd0;
+	builder_maccore_dat_w <= 32'd0;
 	builder_next_state <= builder_state;
 	case (builder_state)
 		1'd1: begin
@@ -2348,9 +2348,9 @@ assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]
 assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err);
 assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));
 always @(*) begin
+	builder_shared_ack <= 1'd0;
 	builder_error <= 1'd0;
 	builder_shared_dat_r <= 32'd0;
-	builder_shared_ack <= 1'd0;
 	builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack);
 	builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r));
 	if (builder_done) begin
@@ -2381,8 +2381,8 @@ always @(*) begin
 end
 assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank0_bus_errors_we <= 1'd0;
 	builder_csrbank0_bus_errors_re <= 1'd0;
+	builder_csrbank0_bus_errors_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin
 		builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we;
 		builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we);
@@ -2411,8 +2411,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank1_sram_writer_length_we <= 1'd0;
 	builder_csrbank1_sram_writer_length_re <= 1'd0;
+	builder_csrbank1_sram_writer_length_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we);
@@ -2429,8 +2429,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_writer_ev_status_re <= 1'd0;
 	builder_csrbank1_sram_writer_ev_status_we <= 1'd0;
+	builder_csrbank1_sram_writer_ev_status_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we);
@@ -2465,8 +2465,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_reader_ready_re <= 1'd0;
 	builder_csrbank1_sram_reader_ready_we <= 1'd0;
+	builder_csrbank1_sram_reader_ready_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we);
@@ -2483,8 +2483,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_reader_slot0_we <= 1'd0;
 	builder_csrbank1_sram_reader_slot0_re <= 1'd0;
+	builder_csrbank1_sram_reader_slot0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we);
@@ -2510,8 +2510,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_reader_ev_pending_we <= 1'd0;
 	builder_csrbank1_sram_reader_ev_pending_re <= 1'd0;
+	builder_csrbank1_sram_reader_ev_pending_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
 		builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we);
@@ -2537,8 +2537,8 @@ always @(*) begin
 end
 assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank1_preamble_errors_we <= 1'd0;
 	builder_csrbank1_preamble_errors_re <= 1'd0;
+	builder_csrbank1_preamble_errors_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
 		builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we);
@@ -2608,8 +2608,8 @@ always @(*) begin
 end
 assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_mdio_r_we <= 1'd0;
 	builder_csrbank2_mdio_r_re <= 1'd0;
+	builder_csrbank2_mdio_r_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
 		builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we;
 		builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we);
@@ -3334,275 +3334,95 @@ end
 assign main_writer_stat_fifo_wrport_dat_r = memdat_1;
 assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr];
 
-reg [13:0] storage_4[0:1];
+reg [31:0] mem[0:381];
-reg [13:0] memdat_2;
-always @(posedge sys_clk) begin
-	if (main_reader_cmd_fifo_wrport_we)
-		storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
-	memdat_2 <= storage_4[main_reader_cmd_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign main_reader_cmd_fifo_wrport_dat_r = memdat_2;
-assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
-
-reg [7:0] mem_grain0[0:381];
 reg [8:0] memadr_4;
-reg [7:0] memdat_3;
+reg [31:0] memdat_2;
 always @(posedge sys_clk) begin
 	if (main_writer_memory0_we)
-		mem_grain0[main_writer_memory0_adr] <= main_writer_memory0_dat_w[7:0];
+		mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w;
 	memadr_4 <= main_writer_memory0_adr;
 end
 
 always @(posedge sys_clk) begin
-	memdat_3 <= mem_grain0[main_sram0_adr0];
+	memdat_2 <= mem[main_sram0_adr0];
 end
 
-assign main_writer_memory0_dat_r[7:0] = mem_grain0[memadr_4];
+assign main_writer_memory0_dat_r = mem[memadr_4];
-assign main_sram0_dat_r0[7:0] = memdat_3;
+assign main_sram0_dat_r0 = memdat_2;
 
-reg [7:0] mem_grain1[0:381];
+reg [31:0] mem_1[0:381];
 reg [8:0] memadr_5;
-reg [7:0] memdat_4;
+reg [31:0] memdat_3;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain1[main_writer_memory0_adr] <= main_writer_memory0_dat_w[15:8];
-	memadr_5 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_4 <= mem_grain1[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[15:8] = mem_grain1[memadr_5];
-assign main_sram0_dat_r0[15:8] = memdat_4;
-
-reg [7:0] mem_grain2[0:381];
-reg [8:0] memadr_6;
-reg [7:0] memdat_5;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain2[main_writer_memory0_adr] <= main_writer_memory0_dat_w[23:16];
-	memadr_6 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_5 <= mem_grain2[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[23:16] = mem_grain2[memadr_6];
-assign main_sram0_dat_r0[23:16] = memdat_5;
-
-reg [7:0] mem_grain3[0:381];
-reg [8:0] memadr_7;
-reg [7:0] memdat_6;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain3[main_writer_memory0_adr] <= main_writer_memory0_dat_w[31:24];
-	memadr_7 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_6 <= mem_grain3[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[31:24] = mem_grain3[memadr_7];
-assign main_sram0_dat_r0[31:24] = memdat_6;
-
-reg [7:0] mem_grain0_1[0:381];
-reg [8:0] memadr_8;
-reg [7:0] memdat_7;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain0_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[7:0];
-	memadr_8 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_7 <= mem_grain0_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[7:0] = mem_grain0_1[memadr_8];
-assign main_sram1_dat_r0[7:0] = memdat_7;
-
-reg [7:0] mem_grain1_1[0:381];
-reg [8:0] memadr_9;
-reg [7:0] memdat_8;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain1_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[15:8];
-	memadr_9 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_8 <= mem_grain1_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[15:8] = mem_grain1_1[memadr_9];
-assign main_sram1_dat_r0[15:8] = memdat_8;
-
-reg [7:0] mem_grain2_1[0:381];
-reg [8:0] memadr_10;
-reg [7:0] memdat_9;
 always @(posedge sys_clk) begin
 	if (main_writer_memory1_we)
-		mem_grain2_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[23:16];
+		mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w;
-	memadr_10 <= main_writer_memory1_adr;
+	memadr_5 <= main_writer_memory1_adr;
 end
 
 always @(posedge sys_clk) begin
-	memdat_9 <= mem_grain2_1[main_sram1_adr0];
+	memdat_3 <= mem_1[main_sram1_adr0];
 end
 
-assign main_writer_memory1_dat_r[23:16] = mem_grain2_1[memadr_10];
+assign main_writer_memory1_dat_r = mem_1[memadr_5];
-assign main_sram1_dat_r0[23:16] = memdat_9;
+assign main_sram1_dat_r0 = memdat_3;
 
-reg [7:0] mem_grain3_1[0:381];
+reg [13:0] storage_4[0:1];
-reg [8:0] memadr_11;
+reg [13:0] memdat_4;
-reg [7:0] memdat_10;
 always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
+	if (main_reader_cmd_fifo_wrport_we)
-		mem_grain3_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[31:24];
+		storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
-	memadr_11 <= main_writer_memory1_adr;
+	memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
-	memdat_10 <= mem_grain3_1[main_sram1_adr0];
 end
 
-assign main_writer_memory1_dat_r[31:24] = mem_grain3_1[memadr_11];
+assign main_reader_cmd_fifo_wrport_dat_r = memdat_4;
-assign main_sram1_dat_r0[31:24] = memdat_10;
+assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
 
-reg [7:0] mem_grain0_2[0:381];
+reg [31:0] mem_2[0:381];
-reg [8:0] memadr_12;
+reg [8:0] memadr_6;
-reg [8:0] memadr_13;
+reg [8:0] memadr_7;
 always @(posedge sys_clk) begin
-	memadr_12 <= main_reader_memory0_adr;
+	memadr_6 <= main_reader_memory0_adr;
 end
 
 always @(posedge sys_clk) begin
 	if (main_sram0_we[0])
-		mem_grain0_2[main_sram0_adr1] <= main_sram0_dat_w[7:0];
+		mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0];
-	memadr_13 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[7:0] = mem_grain0_2[memadr_12];
-assign main_sram0_dat_r1[7:0] = mem_grain0_2[memadr_13];
-
-reg [7:0] mem_grain1_2[0:381];
-reg [8:0] memadr_14;
-reg [8:0] memadr_15;
-always @(posedge sys_clk) begin
-	memadr_14 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
 	if (main_sram0_we[1])
-		mem_grain1_2[main_sram0_adr1] <= main_sram0_dat_w[15:8];
+		mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8];
-	memadr_15 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[15:8] = mem_grain1_2[memadr_14];
-assign main_sram0_dat_r1[15:8] = mem_grain1_2[memadr_15];
-
-reg [7:0] mem_grain2_2[0:381];
-reg [8:0] memadr_16;
-reg [8:0] memadr_17;
-always @(posedge sys_clk) begin
-	memadr_16 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
 	if (main_sram0_we[2])
-		mem_grain2_2[main_sram0_adr1] <= main_sram0_dat_w[23:16];
+		mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16];
-	memadr_17 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[23:16] = mem_grain2_2[memadr_16];
-assign main_sram0_dat_r1[23:16] = mem_grain2_2[memadr_17];
-
-reg [7:0] mem_grain3_2[0:381];
-reg [8:0] memadr_18;
-reg [8:0] memadr_19;
-always @(posedge sys_clk) begin
-	memadr_18 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
 	if (main_sram0_we[3])
-		mem_grain3_2[main_sram0_adr1] <= main_sram0_dat_w[31:24];
+		mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24];
-	memadr_19 <= main_sram0_adr1;
+	memadr_7 <= main_sram0_adr1;
 end
 
-assign main_reader_memory0_dat_r[31:24] = mem_grain3_2[memadr_18];
+assign main_reader_memory0_dat_r = mem_2[memadr_6];
-assign main_sram0_dat_r1[31:24] = mem_grain3_2[memadr_19];
+assign main_sram0_dat_r1 = mem_2[memadr_7];
 
-reg [7:0] mem_grain0_3[0:381];
+reg [31:0] mem_3[0:381];
-reg [8:0] memadr_20;
+reg [8:0] memadr_8;
-reg [8:0] memadr_21;
+reg [8:0] memadr_9;
 always @(posedge sys_clk) begin
-	memadr_20 <= main_reader_memory1_adr;
+	memadr_8 <= main_reader_memory1_adr;
 end
 
 always @(posedge sys_clk) begin
 	if (main_sram1_we[0])
-		mem_grain0_3[main_sram1_adr1] <= main_sram1_dat_w[7:0];
+		mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0];
-	memadr_21 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[7:0] = mem_grain0_3[memadr_20];
-assign main_sram1_dat_r1[7:0] = mem_grain0_3[memadr_21];
-
-reg [7:0] mem_grain1_3[0:381];
-reg [8:0] memadr_22;
-reg [8:0] memadr_23;
-always @(posedge sys_clk) begin
-	memadr_22 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
 	if (main_sram1_we[1])
-		mem_grain1_3[main_sram1_adr1] <= main_sram1_dat_w[15:8];
+		mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8];
-	memadr_23 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[15:8] = mem_grain1_3[memadr_22];
-assign main_sram1_dat_r1[15:8] = mem_grain1_3[memadr_23];
-
-reg [7:0] mem_grain2_3[0:381];
-reg [8:0] memadr_24;
-reg [8:0] memadr_25;
-always @(posedge sys_clk) begin
-	memadr_24 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
 	if (main_sram1_we[2])
-		mem_grain2_3[main_sram1_adr1] <= main_sram1_dat_w[23:16];
+		mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16];
-	memadr_25 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[23:16] = mem_grain2_3[memadr_24];
-assign main_sram1_dat_r1[23:16] = mem_grain2_3[memadr_25];
-
-reg [7:0] mem_grain3_3[0:381];
-reg [8:0] memadr_26;
-reg [8:0] memadr_27;
-always @(posedge sys_clk) begin
-	memadr_26 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
 	if (main_sram1_we[3])
-		mem_grain3_3[main_sram1_adr1] <= main_sram1_dat_w[31:24];
+		mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24];
-	memadr_27 <= main_sram1_adr1;
+	memadr_9 <= main_sram1_adr1;
 end
 
-assign main_reader_memory1_dat_r[31:24] = mem_grain3_3[memadr_26];
+assign main_reader_memory1_dat_r = mem_3[memadr_8];
-assign main_sram1_dat_r1[31:24] = mem_grain3_3[memadr_27];
+assign main_sram1_dat_r1 = mem_3[memadr_9];
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
 	.INIT(1'd1)

liteeth/generated/nexys-video/liteeth_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (--------) on 2021-08-09 13:54:49
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01
 //--------------------------------------------------------------------------------
 module liteeth_core(
 	input wire sys_clock,
@@ -39,16 +39,16 @@ wire main_maccore_maccore_bus_errors_we;
 reg main_maccore_maccore_bus_errors_re = 1'd0;
 wire main_maccore_maccore_bus_error;
 reg [31:0] main_maccore_maccore_bus_errors = 32'd0;
-wire sys_clk;
+(* dont_touch = "true" *) wire sys_clk;
 wire sys_rst;
 wire por_clk;
 reg main_maccore_int_rst = 1'd1;
 reg main_maccore_ethphy_reset_storage = 1'd0;
 reg main_maccore_ethphy_reset_re = 1'd0;
-wire eth_rx_clk;
+(* dont_touch = "true" *) wire eth_rx_clk;
 wire eth_rx_rst;
 wire main_maccore_ethphy_eth_rx_clk_ibuf;
-wire eth_tx_clk;
+(* dont_touch = "true" *) wire eth_tx_clk;
 wire eth_tx_rst;
 wire eth_tx_delayed_clk;
 reg main_maccore_ethphy_reset0 = 1'd0;
@@ -1051,6 +1051,7 @@ assign main_sink_payload_error = main_rx_cdc_source_source_payload_error;
 assign main_ps_preamble_error_i = main_preamble_checker_error;
 assign main_ps_crc_error_i = main_liteethmaccrc32checker_error;
 always @(*) begin
+	main_tx_gap_inserter_source_payload_last_be <= 1'd0;
 	main_tx_gap_inserter_source_payload_error <= 1'd0;
 	main_tx_gap_inserter_sink_ready <= 1'd0;
 	main_tx_gap_inserter_source_valid <= 1'd0;
@@ -1060,7 +1061,6 @@ always @(*) begin
 	main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0;
 	main_tx_gap_inserter_source_last <= 1'd0;
 	main_tx_gap_inserter_source_payload_data <= 8'd0;
-	main_tx_gap_inserter_source_payload_last_be <= 1'd0;
 	builder_liteethmacgap_next_state <= builder_liteethmacgap_state;
 	case (builder_liteethmacgap_state)
 		1'd1: begin
@@ -1163,8 +1163,8 @@ assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink
 always @(*) begin
 	main_preamble_checker_source_payload_error <= 1'd0;
 	main_preamble_checker_error <= 1'd0;
-	main_preamble_checker_sink_ready <= 1'd0;
 	main_preamble_checker_source_valid <= 1'd0;
+	main_preamble_checker_sink_ready <= 1'd0;
 	builder_liteethmacpreamblechecker_next_state <= 1'd0;
 	main_preamble_checker_source_first <= 1'd0;
 	main_preamble_checker_source_last <= 1'd0;
@@ -1445,6 +1445,7 @@ assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_pre
 assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r);
 assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59);
 always @(*) begin
+	builder_liteethmacpaddinginserter_next_state <= 1'd0;
 	main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0;
 	main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0;
 	main_padding_inserter_sink_ready <= 1'd0;
@@ -1454,7 +1455,6 @@ always @(*) begin
 	main_padding_inserter_source_payload_data <= 8'd0;
 	main_padding_inserter_source_payload_last_be <= 1'd0;
 	main_padding_inserter_source_payload_error <= 1'd0;
-	builder_liteethmacpaddinginserter_next_state <= 1'd0;
 	builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state;
 	case (builder_liteethmacpaddinginserter_state)
 		1'd1: begin
@@ -1945,8 +1945,8 @@ always @(*) begin
 	builder_liteethmacsramwriter_next_state <= 3'd0;
 	main_writer_slot_ce <= 1'd0;
 	main_writer_counter_t_next_value <= 32'd0;
-	main_writer_start <= 1'd0;
 	main_writer_counter_t_next_value_ce <= 1'd0;
+	main_writer_start <= 1'd0;
 	main_writer_ongoing <= 1'd0;
 	main_writer_errors_status_f_next_value <= 32'd0;
 	main_writer_stat_fifo_sink_valid <= 1'd0;
@@ -2191,8 +2191,8 @@ assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) |
 always @(*) begin
 	builder_maccore_adr <= 14'd0;
 	builder_maccore_we <= 1'd0;
-	builder_maccore_wishbone_ack <= 1'd0;
 	builder_maccore_dat_w <= 32'd0;
+	builder_maccore_wishbone_ack <= 1'd0;
 	builder_next_state <= 1'd0;
 	builder_maccore_wishbone_dat_r <= 32'd0;
 	builder_next_state <= builder_state;
@@ -2250,8 +2250,8 @@ assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err);
 assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));
 always @(*) begin
 	builder_shared_ack <= 1'd0;
-	builder_shared_dat_r <= 32'd0;
 	builder_error <= 1'd0;
+	builder_shared_dat_r <= 32'd0;
 	builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack);
 	builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r));
 	if (builder_done) begin
@@ -2273,8 +2273,8 @@ always @(*) begin
 end
 assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank0_scratch0_we <= 1'd0;
 	builder_csrbank0_scratch0_re <= 1'd0;
+	builder_csrbank0_scratch0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we;
 		builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we);
@@ -2348,8 +2348,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
 	builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0;
+	builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
 		builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we);
@@ -2357,8 +2357,8 @@ always @(*) begin
 end
 assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_reader_start_start_re <= 1'd0;
 	main_reader_start_start_we <= 1'd0;
+	main_reader_start_start_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
 		main_reader_start_start_re <= builder_interface1_bank_bus_we;
 		main_reader_start_start_we <= (~builder_interface1_bank_bus_we);
@@ -2500,8 +2500,8 @@ always @(*) begin
 end
 assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_mdio_w0_we <= 1'd0;
 	builder_csrbank2_mdio_w0_re <= 1'd0;
+	builder_csrbank2_mdio_w0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we;
 		builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we);
@@ -3451,20 +3451,96 @@ end
 assign main_writer_stat_fifo_wrport_dat_r = memdat_1;
 assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr];
 
+reg [31:0] mem[0:381];
+reg [8:0] memadr_4;
+reg [31:0] memdat_2;
+always @(posedge sys_clk) begin
+	if (main_writer_memory0_we)
+		mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w;
+	memadr_4 <= main_writer_memory0_adr;
+end
+
+always @(posedge sys_clk) begin
+	memdat_2 <= mem[main_sram0_adr0];
+end
+
+assign main_writer_memory0_dat_r = mem[memadr_4];
+assign main_sram0_dat_r0 = memdat_2;
+
+reg [31:0] mem_1[0:381];
+reg [8:0] memadr_5;
+reg [31:0] memdat_3;
+always @(posedge sys_clk) begin
+	if (main_writer_memory1_we)
+		mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w;
+	memadr_5 <= main_writer_memory1_adr;
+end
+
+always @(posedge sys_clk) begin
+	memdat_3 <= mem_1[main_sram1_adr0];
+end
+
+assign main_writer_memory1_dat_r = mem_1[memadr_5];
+assign main_sram1_dat_r0 = memdat_3;
+
 reg [13:0] storage_4[0:1];
-reg [13:0] memdat_2;
+reg [13:0] memdat_4;
 always @(posedge sys_clk) begin
 	if (main_reader_cmd_fifo_wrport_we)
 		storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
-	memdat_2 <= storage_4[main_reader_cmd_fifo_wrport_adr];
+	memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign main_reader_cmd_fifo_wrport_dat_r = memdat_2;
+assign main_reader_cmd_fifo_wrport_dat_r = memdat_4;
 assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
 
+reg [31:0] mem_2[0:381];
+reg [8:0] memadr_6;
+reg [8:0] memadr_7;
+always @(posedge sys_clk) begin
+	memadr_6 <= main_reader_memory0_adr;
+end
+
+always @(posedge sys_clk) begin
+	if (main_sram0_we[0])
+		mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0];
+	if (main_sram0_we[1])
+		mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8];
+	if (main_sram0_we[2])
+		mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16];
+	if (main_sram0_we[3])
+		mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24];
+	memadr_7 <= main_sram0_adr1;
+end
+
+assign main_reader_memory0_dat_r = mem_2[memadr_6];
+assign main_sram0_dat_r1 = mem_2[memadr_7];
+
+reg [31:0] mem_3[0:381];
+reg [8:0] memadr_8;
+reg [8:0] memadr_9;
+always @(posedge sys_clk) begin
+	memadr_8 <= main_reader_memory1_adr;
+end
+
+always @(posedge sys_clk) begin
+	if (main_sram1_we[0])
+		mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0];
+	if (main_sram1_we[1])
+		mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8];
+	if (main_sram1_we[2])
+		mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16];
+	if (main_sram1_we[3])
+		mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24];
+	memadr_9 <= main_sram1_adr1;
+end
+
+assign main_reader_memory1_dat_r = mem_3[memadr_8];
+assign main_sram1_dat_r1 = mem_3[memadr_9];
+
 FD FD(
 	.C(main_maccore_ethphy_clkin),
 	.D(main_maccore_ethphy_reset0),
@@ -3534,262 +3610,6 @@ PLLE2_ADV #(
 	.LOCKED(main_maccore_ethphy_locked)
 );
 
-reg [7:0] mem_grain0[0:381];
-reg [8:0] memadr_4;
-reg [7:0] memdat_3;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain0[main_writer_memory0_adr] <= main_writer_memory0_dat_w[7:0];
-	memadr_4 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_3 <= mem_grain0[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[7:0] = mem_grain0[memadr_4];
-assign main_sram0_dat_r0[7:0] = memdat_3;
-
-reg [7:0] mem_grain1[0:381];
-reg [8:0] memadr_5;
-reg [7:0] memdat_4;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain1[main_writer_memory0_adr] <= main_writer_memory0_dat_w[15:8];
-	memadr_5 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_4 <= mem_grain1[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[15:8] = mem_grain1[memadr_5];
-assign main_sram0_dat_r0[15:8] = memdat_4;
-
-reg [7:0] mem_grain2[0:381];
-reg [8:0] memadr_6;
-reg [7:0] memdat_5;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain2[main_writer_memory0_adr] <= main_writer_memory0_dat_w[23:16];
-	memadr_6 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_5 <= mem_grain2[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[23:16] = mem_grain2[memadr_6];
-assign main_sram0_dat_r0[23:16] = memdat_5;
-
-reg [7:0] mem_grain3[0:381];
-reg [8:0] memadr_7;
-reg [7:0] memdat_6;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain3[main_writer_memory0_adr] <= main_writer_memory0_dat_w[31:24];
-	memadr_7 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_6 <= mem_grain3[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[31:24] = mem_grain3[memadr_7];
-assign main_sram0_dat_r0[31:24] = memdat_6;
-
-reg [7:0] mem_grain0_1[0:381];
-reg [8:0] memadr_8;
-reg [7:0] memdat_7;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain0_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[7:0];
-	memadr_8 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_7 <= mem_grain0_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[7:0] = mem_grain0_1[memadr_8];
-assign main_sram1_dat_r0[7:0] = memdat_7;
-
-reg [7:0] mem_grain1_1[0:381];
-reg [8:0] memadr_9;
-reg [7:0] memdat_8;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain1_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[15:8];
-	memadr_9 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_8 <= mem_grain1_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[15:8] = mem_grain1_1[memadr_9];
-assign main_sram1_dat_r0[15:8] = memdat_8;
-
-reg [7:0] mem_grain2_1[0:381];
-reg [8:0] memadr_10;
-reg [7:0] memdat_9;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain2_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[23:16];
-	memadr_10 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_9 <= mem_grain2_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[23:16] = mem_grain2_1[memadr_10];
-assign main_sram1_dat_r0[23:16] = memdat_9;
-
-reg [7:0] mem_grain3_1[0:381];
-reg [8:0] memadr_11;
-reg [7:0] memdat_10;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain3_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[31:24];
-	memadr_11 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_10 <= mem_grain3_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[31:24] = mem_grain3_1[memadr_11];
-assign main_sram1_dat_r0[31:24] = memdat_10;
-
-reg [7:0] mem_grain0_2[0:381];
-reg [8:0] memadr_12;
-reg [8:0] memadr_13;
-always @(posedge sys_clk) begin
-	memadr_12 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[0])
-		mem_grain0_2[main_sram0_adr1] <= main_sram0_dat_w[7:0];
-	memadr_13 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[7:0] = mem_grain0_2[memadr_12];
-assign main_sram0_dat_r1[7:0] = mem_grain0_2[memadr_13];
-
-reg [7:0] mem_grain1_2[0:381];
-reg [8:0] memadr_14;
-reg [8:0] memadr_15;
-always @(posedge sys_clk) begin
-	memadr_14 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[1])
-		mem_grain1_2[main_sram0_adr1] <= main_sram0_dat_w[15:8];
-	memadr_15 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[15:8] = mem_grain1_2[memadr_14];
-assign main_sram0_dat_r1[15:8] = mem_grain1_2[memadr_15];
-
-reg [7:0] mem_grain2_2[0:381];
-reg [8:0] memadr_16;
-reg [8:0] memadr_17;
-always @(posedge sys_clk) begin
-	memadr_16 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[2])
-		mem_grain2_2[main_sram0_adr1] <= main_sram0_dat_w[23:16];
-	memadr_17 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[23:16] = mem_grain2_2[memadr_16];
-assign main_sram0_dat_r1[23:16] = mem_grain2_2[memadr_17];
-
-reg [7:0] mem_grain3_2[0:381];
-reg [8:0] memadr_18;
-reg [8:0] memadr_19;
-always @(posedge sys_clk) begin
-	memadr_18 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[3])
-		mem_grain3_2[main_sram0_adr1] <= main_sram0_dat_w[31:24];
-	memadr_19 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[31:24] = mem_grain3_2[memadr_18];
-assign main_sram0_dat_r1[31:24] = mem_grain3_2[memadr_19];
-
-reg [7:0] mem_grain0_3[0:381];
-reg [8:0] memadr_20;
-reg [8:0] memadr_21;
-always @(posedge sys_clk) begin
-	memadr_20 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[0])
-		mem_grain0_3[main_sram1_adr1] <= main_sram1_dat_w[7:0];
-	memadr_21 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[7:0] = mem_grain0_3[memadr_20];
-assign main_sram1_dat_r1[7:0] = mem_grain0_3[memadr_21];
-
-reg [7:0] mem_grain1_3[0:381];
-reg [8:0] memadr_22;
-reg [8:0] memadr_23;
-always @(posedge sys_clk) begin
-	memadr_22 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[1])
-		mem_grain1_3[main_sram1_adr1] <= main_sram1_dat_w[15:8];
-	memadr_23 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[15:8] = mem_grain1_3[memadr_22];
-assign main_sram1_dat_r1[15:8] = mem_grain1_3[memadr_23];
-
-reg [7:0] mem_grain2_3[0:381];
-reg [8:0] memadr_24;
-reg [8:0] memadr_25;
-always @(posedge sys_clk) begin
-	memadr_24 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[2])
-		mem_grain2_3[main_sram1_adr1] <= main_sram1_dat_w[23:16];
-	memadr_25 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[23:16] = mem_grain2_3[memadr_24];
-assign main_sram1_dat_r1[23:16] = mem_grain2_3[memadr_25];
-
-reg [7:0] mem_grain3_3[0:381];
-reg [8:0] memadr_26;
-reg [8:0] memadr_27;
-always @(posedge sys_clk) begin
-	memadr_26 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[3])
-		mem_grain3_3[main_sram1_adr1] <= main_sram1_dat_w[31:24];
-	memadr_27 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[31:24] = mem_grain3_3[memadr_26];
-assign main_sram1_dat_r1[31:24] = mem_grain3_3[memadr_27];
-
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
 	.INIT(1'd1)
 ) FDPE (

microwatt.core

@@ -106,6 +106,12 @@ filesets:
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 
+  wukong-v2:
+    files:
+      - fpga/wukong-v2.xdc : {file_type : xdc}
+      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-wukong-v2.vhdl : {file_type : vhdlSource-2008}
+
   cmod_a7-35:
     files:
       - fpga/cmod_a7-35.xdc : {file_type : xdc}
@@ -338,6 +344,50 @@ targets:
       vivado: {part : xc7a100ticsg324-1L}
     toplevel : toplevel
 
+  wukong-v2-a100t-nodram:
+    default_tool: vivado
+    filesets: [core, wukong-v2, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
+    parameters:
+      - memory_size
+      - ram_init_file
+      - use_litedram=false
+      - use_liteeth=false
+      - use_litesdcard=true
+      - disable_flatten_core
+      - spi_flash_offset=4194304
+      - clk_frequency=100000000
+      - log_length=2048
+      - uart_is_16550
+      - has_fpu
+      - has_btc
+      - has_short_mult
+    generate: [litesdcard_wukong-v2]
+    tools:
+      vivado: {part : xc7a100tfgg676-1}
+    toplevel : toplevel
+
+  wukong-v2-a100t:
+    default_tool: vivado
+    filesets: [core, wukong-v2, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
+    parameters:
+      - memory_size=0
+      - ram_init_file
+      - use_litedram=true
+      - use_liteeth=true
+      - use_litesdcard=true
+      - disable_flatten_core
+      - no_bram=true
+      - spi_flash_offset=4194304
+      - log_length=0
+      - uart_is_16550
+      - has_fpu
+      - has_btc
+      - has_short_mult
+    generate: [litedram_wukong-v2, liteeth_wukong-v2, litesdcard_wukong-v2]
+    tools:
+      vivado: {part : xc7a100tfgg676-1}
+    toplevel : toplevel
+
   cmod_a7-35:
     default_tool: vivado
     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
@@ -395,6 +445,18 @@ generate:
     generator: litedram_gen
     parameters: {board : genesys2}
 
+  litedram_wukong-v2:
+    generator: litedram_gen
+    parameters: {board : wukong-v2}
+
+  liteeth_wukong-v2:
+    generator: liteeth_gen
+    parameters: {board : wukong-v2}
+
+  litesdcard_wukong-v2:
+    generator: litesdcard_gen
+    parameters: {vendor : xilinx}
+
 parameters:
   memory_size:
     datatype    : int