Reformat simple_ram_behavioural

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
jtag-port
Anton Blanchard 5 years ago committed by Anton Blanchard
parent fd9e971b2c
commit 1d5e8c2eb4

@ -18,8 +18,16 @@ architecture behave of simple_ram_behavioural_tb is
signal w_out : wishbone_master_out;
begin
simple_ram_0: entity work.mw_soc_memory
generic map ( RAM_INIT_FILE => "simple_ram_behavioural_tb.bin", MEMORY_SIZE => 16 )
port map (clk => clk, rst => rst, wishbone_out => w_in, wishbone_in => w_out);
generic map (
RAM_INIT_FILE => "simple_ram_behavioural_tb.bin",
MEMORY_SIZE => 16
)
port map (
clk => clk,
rst => rst,
wishbone_out => w_in,
wishbone_in => w_out
);

clock: process
begin

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