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@ -11,7 +11,7 @@ all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb
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all: $(all)
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%.o : %.vhdl
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$(GHDL) -a $(GHDLFLAGS) $<
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$(GHDL) -a $(GHDLFLAGS) --workdir=$(shell dirname $@) $<
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common.o: decode_types.o
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control.o: gpr_hazard.o cr_hazard.o common.o
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@ -72,7 +72,7 @@ sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
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fpga/soc_reset_tb.o: fpga/soc_reset.o
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soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
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$(GHDL) -e $(GHDLFLAGS) soc_reset_tb
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$(GHDL) -e $(GHDLFLAGS) --workdir=fpga soc_reset_tb
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core_tb: core_tb.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
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@ -130,6 +130,7 @@ test_micropython_long: core_tb
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clean:
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rm -f *.o work-*cf unisim-*cf $(all)
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rm -f fpga/*.o fpga/work-*cf
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rm -f sim-unisim/*.o sim-unisim/unisim-*cf
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distclean: clean
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